R1EV5801MB Series

R10DS0209EJ0200 Rev.2.00

Page 6 of 20

May 12, 2016

AC Characteristics

(Ta = -40 to +85

Test Conditions

 Input pulse levels:

0.4 V to 2.4 V,

 Input rise and fall time:  20 ns

 Output load: 1TTL Gate +100 pF

 Reference levels for measuring timing: 0.8 V, 2.0 V

Read Cycle

Parameter

Symbol

Min

Max

Unit

Test conditions

Address to output delay



250

ns

CE to output delay



250

ns

OE to output delay

10

120

ns

Address to output hold

0



ns

0

50

ns

0

350

ns

RES to output delay

0

600

ns

Write Cycle

Parameter

Symbol

Min*

2

Typ

Max

Unit

Test conditions

Address setup time

0





ns

Address hold time

150





ns

CE to write setup time (WE controlled)

0





ns

CE hold time (WE controlled)

0





ns

WE to write setup time (CE controlled)

0





ns

WE hold time (CE controlled)

0





ns

OE to write setup time

0





ns

OE hold time

0





ns

Data setup time

100





ns

Data hold time

10





ns

WE pulse width (WE controlled)

0.250



30

µs

CE pulse width (CE controlled)

0.250



30

µs

Data latch time

750





ns

Byte load cycle

1.0



30

s

Byte load window

100





s

Write cycle time





10*

3

ms

Time to device busy

120





ns

Write start time

250*

4





ns

Reset protect time

100





s

Reset high time*

5

1





s

driven.

2. Use this device in longer cycle than this value.

completes the internal write operation within this value.

5. This parameter is sampled and not 100

 tested.

6. A7 through A16 are page addresses and these addresses are latched at the first falling edge of

WE.

7. A7 through A16 are page addresses and these addresses are latched at the first falling edge of

CE.

8. See AC read characteristics.