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R1EV5801MB Datasheet(PDF) 6 Page - Renesas Technology Corp |
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R1EV5801MB Datasheet(HTML) 6 Page - Renesas Technology Corp |
6 / 22 page R1EV5801MB Series R10DS0209EJ0200 Rev.2.00 Page 6 of 20 May 12, 2016 AC Characteristics (Ta = -40 to +85 C, VCC = 2.7 V to 5.5 V) Test Conditions Input pulse levels: 0.4 V to 2.4 V, 0 V to VCC (RES pin) Input rise and fall time: 20 ns Output load: 1TTL Gate +100 pF Reference levels for measuring timing: 0.8 V, 2.0 V Read Cycle Parameter Symbol Min Max Unit Test conditions Address to output delay tACC 250 ns CE = OE = VIL, WE = VIH CE to output delay tCE 250 ns OE = VIL, WE = VIH OE to output delay tOE 10 120 ns CE = VIL, WE = VIH Address to output hold tOH 0 ns CE = OE = VIL, WE = VIH OE (CE) high to output float*1 tDF 0 50 ns CE = VIL, WE = VIH RES low to output float*1 tDFR 0 350 ns CE = OE = VIL, WE = VIH RES to output delay tRR 0 600 ns CE = OE = VIL, WE = VIH Write Cycle Parameter Symbol Min* 2 Typ Max Unit Test conditions Address setup time tAS 0 ns Address hold time tAH 150 ns CE to write setup time (WE controlled) tCS 0 ns CE hold time (WE controlled) tCH 0 ns WE to write setup time (CE controlled) tWS 0 ns WE hold time (CE controlled) tWH 0 ns OE to write setup time tOES 0 ns OE hold time tOEH 0 ns Data setup time tDS 100 ns Data hold time tDH 10 ns WE pulse width (WE controlled) tWP 0.250 30 µs CE pulse width (CE controlled) tCW 0.250 30 µs Data latch time tDL 750 ns Byte load cycle tBLC 1.0 30 s Byte load window tBL 100 s Write cycle time tWC 10* 3 ms Time to device busy tDB 120 ns Write start time tDW 250* 4 ns Reset protect time tRP 100 s Reset high time* 5 tRES 1 s Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. Use this device in longer cycle than this value. 3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used. 5. This parameter is sampled and not 100 tested. 6. A7 through A16 are page addresses and these addresses are latched at the first falling edge of WE. 7. A7 through A16 are page addresses and these addresses are latched at the first falling edge of CE. 8. See AC read characteristics. |
Similar Part No. - R1EV5801MB_16 |
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Similar Description - R1EV5801MB_16 |
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