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R5F524TBADFP Datasheet(PDF) 4 Page - Renesas Technology Corp |
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R5F524TBADFP Datasheet(HTML) 4 Page - Renesas Technology Corp |
4 / 133 page R01DS0257EJ0200 Rev.2.00 Page 4 of 133 Apr 14, 2017 RX24T Group 1. Overview Timers General PWM timer (GPTB) • 16 bits × 4 channels • Two channels can be cascaded and used as a 32-bit timer • Counting up or down (saw waves), or counting up and down (triangle waves) is selectable for each counter. • A count clock is selectable from 13 types (PCLK/1, PCLK/2, PCLK/4, PCLK/8, PCLK/16,PCLK/32, PCLK/64, PCLK/256, PCLK/1024, GTECLKA, GTECLKB, GTECLKC, and GTECLKD) for each channel. • Two I/O pins per channel • Two output compare/input capture registers per channel • For the two output compare/input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. • In output compare operation, buffer switching can be at crests or troughs, enabling the generation of laterally asymmetric PWM waveforms. • Registers for setting up frame cycles in each channel (with capability for generating interrupts at overflow or underflow) • Synchronous operation of the several counters • Modes of synchronous operation (synchronized or displaced by a desired time to obtain relative phase shifts) • Generation of dead times in PWM operation • Through combination of three counters, generation of three-phased PWM waveforms incorporating dead times • Starting, clearing, and stopping counters in response to external or internal triggers • Internal trigger sources: output of the comparator detection, MTU3 count start, software, compare match • Noise filter function for signals on the Input capture, external trigger pins, and the external count clock pins • A/D converter start triggers can be generated Compare match timer (CMT) • (16 bits × 2 channels) × 2 units • Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512) Independent watchdog timer (IWDTa) • 14 bits × 1 channel • Count clock: Dedicated low-speed on-chip oscillator for the IWDT-dedicated on-chip oscillator Frequency divided by 1, 16, 32, 64, 128, or 256 8-bit timer (TMR) • (8 bits × 2 channels) × 4 units • Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192) and an external clock can be selected • Pulse output and PWM output with any duty cycle are available • Two channels can be cascaded and used as a 16-bit timer • Generates A/D conversion start trigger • Generates baud rate clock for the SCI5 and SCI6 Communication functions Serial communications interfaces (SCIg) • 3 channels (channel 1, 5, and 6: SCIg) • SCIg Serial communications: asynchronous, clock synchronous, and smart-card interface On-chip baud rate generator allows selection of the desired bit rate Selection of LSB-first or MSB first transfer Average transfer rate clocks for SCI5 and SCI6 can be input from TMR timers Simple I2C Simple SPI Multi-processor function Detection of the start bit: Level or edge is selectable. 9-bit transfer mode Bit rate modulation I2C bus interface (RIICa) • 1 channel • Communications formats: I2C bus format/SMBus format • Master mode or slave mode selectable • Supports fast mode CAN module (RSCAN) • Single channel • ISO11898-1 specifications compliant (standard and extended frames) • 16 message boxes Serial peripheral interface (RSPIb) • 1 channel • Transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) • Capable of handling serial transfer as a master or slave • Data formats Choice of LSB-first or MSB-first transfer The number of bits in each transfer can be changed to 8 to 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) • Double buffers for both transmission and reception Table 1.1 Outline of Specifications (3/4) Classification Module/Function Description |
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