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R1LV1616HSA-4SI Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R1LV1616HSA-4SI Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 21 page  R1LV1616HSA-I Series Rev.1.02, Feb.23.2017, page 11 of 19 Read Cycle R1LV1616HSA-I -4SI -5SI Parameter Symbol Min Max Min Max Unit Notes Read cycle time tRC 45 55 ns Address access time tAA 45 55 ns Chip select access time tACS1 45 55 ns tACS2 45 55 ns Output enable to output valid tOE 30 35 ns Output hold from address change tOH 10 10 ns LB#, UB# access time tBA 45 55 ns Chip select to output in low-Z tCLZ1 10 10 ns 2, 3 tCLZ2 10 10 ns 2, 3 LB#, UB# enable to low-Z tBLZ 5 5 ns 2, 3 Output enable to output in low-Z tOLZ 5 5 ns 2, 3 Chip deselect to output in high-Z tCHZ1 0 20 0 20 ns 1, 2, 3 tCHZ2 0 20 0 20 ns 1, 2, 3 LB#, UB# disable to high-Z tBHZ 0 15 0 20 ns 1, 2, 3 Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2, 3 Write Cycle R1LV1616HSA-I -4SI -5SI Parameter Symbol Min Max Min Max Unit Notes Write cycle time tWC 45 55 ns Address valid to end of write tAW 45 50 ns Chip selection to end of write tCW 45 50 ns 5 Write pulse width tWP 35 40 ns 4 LB#, UB# valid to end of write tBW 45 50 ns Address setup time tAS 0 0 ns 6 Write recovery time tWR 0 0 ns 7 Data to write time overlap tDW 25 25 ns Data hold from write time tDH 0 0 ns Output active from end of write tOW 5 5 ns 2 Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2 Write to output in high-Z tWHZ 0 15 0 20 ns 1, 2 |
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