72T36125L6-7BB datasheet(5/56 Pages) IDT

Part #	72T36125L6-7BB

Description	2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

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Manufacturer	IDT [Integrated Device Technology]

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COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T36105/115/125 2.5V TeraSync

™

™ 36-BIT FIFO

64K x 36, 128K x 36 and 256K x 36

BM

I W

OW

Write Port Width

Read Port Width

L

x36

H

L

x36

x18

H

L

H

x36

x9

H

L

x18

x36

H

x9

x36

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

NOTE:

1. Pin status during Master Reset.

Figure 1. Single Device Configuration Signal Flow Diagram

(x36, x18, x9) DATA OUT (Q0 - Qn)

(x36, x18, x9) DATA IN (D0 - Dn)

MASTER RESET (

MRS)

READ CLOCK (RCLK/RD)

READ ENABLE (

REN)

OUTPUT ENABLE (

OE)

EMPTY FLAG/OUTPUT READY (

EF/OR)

PROGRAMMABLE ALMOST-EMPTY (

PAE)

WRITE CLOCK (WCLK/WR)

WRITE ENABLE (

WEN)

LOAD (

LD)

FULL FLAG/INPUT READY (

FF/IR)

PROGRAMMABLE ALMOST-FULL (

PAF)

IDT

72T36105

72T36115

72T36125

PARTIAL RESET (

PRS)

FIRST WORD FALL

THROUGH/

SERIAL INPUT (FWFT/SI)

RETRANSMIT (

RT)

5907 drw03

HALF-FULL FLAG (

HF)

SERIAL ENABLE(

SEN)

INPUT WIDTH (IW)

OUTPUT WIDTH (OW)

BIG-ENDIAN/LITTLE-ENDIAN (

BE)

INTERSPERSED/

NON-INTERSPERSED PARITY (IP)

BUS-

MATCHING

(BM)

SERIAL CLOCK (SCLK)

MARK

READ CHIP SELECT (

RCS)

RCLK ECHO, ERCLK

REN ECHO, EREN

WRITE CHIP SELECT (

WCS)

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72T36125L6-7BB Datasheet(PDF) 5 Page - Integrated Device Technology

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