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LTC3733CUHF-1 Datasheet(PDF) 9 Page - Linear Technology |
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LTC3733CUHF-1 Datasheet(HTML) 9 Page - Linear Technology |
9 / 32 page 9 LTC3733/LTC3733-1 3733f PI FU CTIO S (G36/QFN) TG1 to TG3 (Pins 33, 30, 22/Pins 32, 29, 20): High Current Gate Drives for Top N-channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to the boost voltage source superimposed on the switch node voltage SW. BOOST1 to BOOST3 (Pins 34, 31, 21/Pins 33, 30, 19): Positive Supply Pins to the Topside Floating Drivers. Bootstrapped capacitors, charged with external Schottky diodes and a boost voltage source, are connected between the BOOST and SW pins. Voltage swing at the BOOST pins is from boost source voltage (typically VCC) to this boost source voltage + VIN (where VIN is the external MOSFET supply rail). PGOOD (Pin 35/Pin 34): This open-drain output is pulled low when the output voltage is outside the PGOOD toler- ance window. PGOOD is blanked during VID transitions for approximately 120 µs. PLLIN (NA/Pin 38): Synchronization Input to Phase De- tector. This pin is internally terminated to SGND with 50k Ω. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. This pin is not available in the G36 package. Exposed Pad (NA/Pin 39): Signal Ground. Must be sol- dered to PCB. |
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