LTC2053

10

2053fa

APPLICATIO S I FOR ATIO

charging current decays exponentially during each input

voltage disturbance due to these currents settles before

the end of the sampling period, there will be no errors

due to source resistance or the source resistance mis-

DC errors occur due to this input current.

In the Typical Performance Characteristics section of this

data sheet, there are curves showing the additional error

from non-zero source resistance in the inputs. If there are

no large capacitors across the inputs, the amplifier is less

sensitive to source resistance and source resistance mis-

match. When large capacitors are placed across the in-

puts, the input charging currents described above result in

larger DC errors, especially with source resistor mis-

matches.

Power Supply Bypassing

The LTC2053 uses a sampled data technique and therefore

contains some clocked digital circuitry. It is therefore

sensistive to supply bypassing. For single or dual supply

operation, a 0.1

µF ceramic capacitor must be connected

possible.

–

+

–

+

3

8

5V

4

5

6

7

2

–

+

–

+

–5V

3

2053 F01

8

5V

SINGLE SUPPLY, UNITY GAIN

DUAL SUPPLY

4

5

6 R2

R1

7

2

R2

R1

()

Settling Time

The sampling rate is 3kHz and the input sampling period

of accuracy at the op amp noninverting input after N clock

cycles or 333

µs(N). The settling time at the OUT pin is also

affected by the settling of the internal op amp. Since the

gain bandwidth of the internal op amp is typically 200kHz,

the settling time is dominated by the switched capacitor

front end for gains below 100 (see Typical Performance

Characteristics).

Input Current

an input charging current during each input sampling

the input current would go to zero for DC inputs.

In reality, there are additional parasitic capacitors which

voltage. For example, the parasitic bottom plate capacitor

the voltage on the –IN pin every cycle. The resulting input

Figure 1