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LM2657MTC Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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LM2657MTC Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 26 page Typical Application (Channel 2 in parenthesis) (Continued) Connection Diagram 20134702 Top View Ordering Information Order Number Package Drawing Supplied As LM2657MTC MTC28 48 Units/Rail LM2657MTCX MTC28 2500 Units/13" Reel Pin Description Pin 1, SENSE1: Output voltage sense pin for Channel 1. It is tied directly to the output rail. The SENSE pin voltage is used by the IC, together with the VIN voltage (Pin 22) to calculate the CCM (continuous conduction mode) duty cycle. This is used by the IC to set the minimum duty cycle in the SKIP mode to 85% of the CCM value. It is also used to set the adaptive duty cycle clamp (see Pin 3). Pin 2, FB1: Feedback pin for Channel 1. This is the inverting input of the channel’s error amplifier. The voltage on this pin under regulation is nominally at 0.6V. A ‘Power Good win- dow’ on this pin determines if the output voltage is within regulation limits (±13%). If the voltage (on either channel) falls outside this window for more than 7µs, ‘Power Not Good’ is signaled on the PGOOD pin (Pin 9). Additionally, if the FB voltage is above the upper limit, an over-voltage fault condition occurs which turns on the low-side FET. The part will resume normal operation on the next high side cycle in which no fault is detected. When single channel operation is desired (one channel is used, the other is disabled), the feedback pins of both channels must be connected together, near the IC. All other pins specific to the unused channel should be left floating (not connected to each other, either). Pin 3, COMP1: Compensation pin for Channel 1. This is the output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to set the duty cycle for normal regulation. Since the Feedback pin is the inverting input of the same error amplifier, the appropri- ate control loop compensation components are placed be- tween this pin and the Feedback pin. The COMP pin is internally pulled low during Soft-start to limit the duty cycle. Once Soft-start is completed, the voltage on this pin can take up the value required to maintain output regulation. Note that an internal voltage clamp does not allow the pin to go much higher than the steady-state requirement. This forms the ‘adaptive duty cycle clamp’ circuit, which serves to limit the maximum allowable duty cycle and peak currents under sudden overloads. Also note that this clamp has been de- signed with enough ‘headroom’ to permit an adequate re- sponse to step loads within normal operating range. Pin 4, SS1: Channel 1 Soft-start pin. A Soft-start capacitor is placed between this pin and ground. A typical capacitance of 0.1µF is recommended. During startup using chip Enable/ power-up, soft-start is reset by connecting an internal 1.8 k Ω resistor between this pin and ground (R SS_DCHG, see Elec- trical Characteristics table). It discharges any remaining charge on the Soft-start capacitors to ensure that the voltage on both Soft-start pins is below 100mV. Reset having thus been obtained, an 11µA current source at this pin charges up the Soft-start capacitor. The voltage on this pin controls the maximum duty cycle, and this produces a gradual ramp-up of the output voltage, thereby preventing large inrush cur- rents into the output capacitors. The voltage on this pin finally clamps close to 5V. During current limit, V DD UVLO, or V IN UVLO this pin is connected to an internal 115µA current sink whenever a current limit event is in progress. This sink current quickly discharges the Soft-start capacitor and forces the duty cycle low to protect the power components. Pin 5, VDD: 5V supply rail for the control and logic sections of both channels. For normal operation to start, the voltage on this pin must be brought above 4.5V. Subsequently, the voltage on this pin (including any ripple component) should not be allowed to fall below 4V for a duration longer than 7µs. Since this pin is also the supply rail for the internal control sections, it should be well-decoupled particularly at high frequencies. A minimum 0.1µF-0.47µF (ceramic) capacitor should be placed on the component side very close to the IC www.national.com 2 |
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