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HD4074849FS Datasheet(PDF) 11 Page - Hitachi Semiconductor |
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HD4074849FS Datasheet(HTML) 11 Page - Hitachi Semiconductor |
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11 / 125 page  HD404849 Series 11 IE IM LSON IAOF IF ICSF ICEF RAME RSP WDON ADSF Not used DTON SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Inhibited Allowed Not executed Inhibited Allowed Inhibited Allowed Not executed in active mode Allowed Allowed Used in subactive mode Not executed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST cannot be guaranteed. Bits in the interrupt control bits area and register flag area can be set and reset by the SEM/SEMD and REM/REMD instructions, and tested with the TM/TMD instructions. Other instructions have no effect on these bits. Note the following restrictions for each bit. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions |
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