6

IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO

256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16

INDUSTRIAL

TEMPERATURERANGE

RS

REN, WEN

HF

OE = 0

OE = 1

6359 drw04

RCLK, WCLK

FF

EF

IDT Standard Mode

(2)

(1)

IDT Standard Mode

NOTES:

1. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.

2. After reset, the outputs will be LOW if

OE = 0 and high-impedanced if OE = 1.

NOTE:

edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the

FF deassertion time may be delayed an extra WCLK cycle.

Figure 3. Full Flag Timing

WEN

RCLK

FF

REN

DATA READ

NEXT DATA READ

DATA IN OUTPUT REGISTER

LOW

OE

DATA WRITE

6359 drw24

WCLK

NO WRITE

1

2

1

2

NO WRITE

Wd

(1)

(1)