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MC68HC908BD48 Datasheet(PDF) 11 Page - Motorola, Inc |
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MC68HC908BD48 Datasheet(HTML) 11 Page - Motorola, Inc |
11 / 290 page Table of Contents MC68HC908BD48 — Rev. 1.0 Technical Data MOTOROLA Table of Contents 11 13.5.2 USB Interrupt Register (UINTR). . . . . . . . . . . . . . . . . . . . . 166 13.5.3 USB Interrupt Register 1 (UIR1). . . . . . . . . . . . . . . . . . . . . 169 13.5.4 USB Control Register 0 (UCR0). . . . . . . . . . . . . . . . . . . . . 171 13.5.5 USB Control Register 1 (UCR1). . . . . . . . . . . . . . . . . . . . . 172 13.5.6 USB Control Register 2 (UCR2). . . . . . . . . . . . . . . . . . . . . 174 13.5.7 USB Status Register (USR) . . . . . . . . . . . . . . . . . . . . . . . . 175 13.5.8 USB Endpoint 0 Data Registers 0 to 7 (UD0R0–UD0R7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13.5.9 USB Endpoint 1/2 Data Registers 0 to 7 (UD1R0–UD1R7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Section 14. Multi-Master IIC Interface (MMIIC) 14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14.4 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14.5 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.5.1 Multi-Master IIC Address Register (MMADR) . . . . . . . . . . 182 14.5.2 Multi-Master IIC Control Register (MMCR) . . . . . . . . . . . . 183 14.5.3 Multi-Master IIC Master Control Register (MIMCR) . . . . . . 184 14.5.4 Multi-Master IIC Status Register (MMSR) . . . . . . . . . . . . . 186 14.5.5 Multi-Master IIC Data Transmit Register (MMDTR) . . . . . . 188 14.5.6 Multi-Master IIC Data Receive Register (MMDRR) . . . . . . 189 14.6 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 190 Section 15. DDC12AB Interface 15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.4 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 15.5 DDC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 |
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