TPS2206A

SLVS449 – DECEMBER 2002

www.ti.com

4

ELECTRICAL CHARACTERISTICS Continued

TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted)

LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I

(1)

RESET = 5.5 V

–1

1

II(RESET)(1)

RESET = 0 V

–30

–20

–10

I (S

)

(1)

SHDN = 5.5 V

–1

1

II

Input current, logic

II(SHDN)(1)

SHDN = 0 V

–50

–3

µA

II

In ut current, logic

I

(1)

LATCH = 5.5 V

50

µA

II(LATCH)(1)

LATCH = 0 V

–1

1

II(CLOCK, DATA)

0 V to 5.5 V

–1

1

VIH

High-level input voltage, logic

2

V

VIL

Low-level input voltage, logic

0.8

V

VO(sat)

Output saturation voltage at OC

IO = 2 mA

0.14

0.4

V

Ilkg

Leakage current at OC

VO(/OC) = 5.5 V

0

1

µA

(1) LATCH has low current pulldown. RESET and SHDN have low-current pullup.

UVLO AND POR (POWER-ON RESET)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VI(3.3V)

Input voltage at 3.3V pin, UVLO

3.3-V level below which all switches are Hi-Z

2.4

2.7

2.9

V

Vhys(3.3V)

UVLO hysteresis voltage at VA (1)

100

mV

VI(5V)

Input voltage at 5V pin, UVLO

5-V level below which only 5V switches are Hi-Z

2.3

2.5

2.9

V

Vhys(5V)

UVLO hysteresis voltage at 5 V(1)

100

mV

tdf

Delay time for falling response, UVLO(1)

Delay from voltage hit (step from 3 V to 2.3 V)

to Hi-Z control (90% VG to GND)

4

µs

VI(POR)

Input voltage, power-on reset(1)

3.3-V voltage below which POR is asserted

causing a RESET internally with all line

switches open and all discharge switches

closed.

1.7

V

(1) Specified by design; not tested in production.