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PACVGA105 Datasheet(PDF) 1 Page - ON Semiconductor |
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PACVGA105 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 6 page Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. 3 1 Publication Order Number: PACVGA105/D PACVGA105 VGA Port Companion Circuit Product Description The PACVGA105 incorporates 7 channels of ESD protection for signal lines commonly found in a VGA port for PCs. ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents associated with the IEC−1000−4−2 Level−4 ESD Protection Standard (8 kV contact discharge). When the channels are subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the positive supply rails or ground where they may be safely dissipated. The upper ESD diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5 V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance. Two non−inverting buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers will accept TTL input levels and convert them to CMOS output levels that swing between GND and VCC. These drivers have a nominal 60 W output impedance to match the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers also have high impedance pull−ups (50 k W nom.) pulling up to the VAUX rail. In addition, the DDC_CLOCK and DDC_DATA channels have 1.8 k W resistors pulling these inputs up to the main 5 V (VCC) rail. Features Seven Channels of ESD Protection Designed to Meet IEC−1000−4−2 Level−4 ESD Requirements (8 kV Contact Discharge) Very Low Loading Capacitance from ESD Protection Diodes at Less than 5 pF Typical TTL to CMOS Level−Translating Buffers for the HSYNC and VSYNC Lines Three Independent Supply Pins (VCC, VRGB and VAUX) to Facilitate Operation with Sub−Micron Graphics Controller ICs High impedance Pull−Ups (50 kW Nominal to VAUX) for HSYNC and VSYNC Inputs Pull−Up Resistors (1.8 kW Nominal to VCC) for DDC_CLK and DDC_DATA Lines Compact 16−Pin QSOP Package These Devices are Pb−Free and are RoHS Compliant Applications ESD Protection and Termination Resistors for VGA (Video) Port Interfaces Desktop PCs Notebook Computers LCD Monitors http://onsemi.com MARKING DIAGRAM Device Package Shipping† ORDERING INFORMATION PACVGA105QR QSOP16 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. QSOP16 QR SUFFIX CASE 492 PACVGA105QR = Specific Device Code YY = Year WW = Work Week G = Pb−Free Package PACVGA 105QR YYWWG |
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