PACVGA201

http://onsemi.com

5

APPLICATION INFORMATION

Figure 1. Typical Connection Diagram

11

GND

H−Sync

V−Sync

DDC_Data

DDC_Clk

Red

Green

Blue

H−Sync

V−Sync

DDC_Data

DDC_Clk

Red

Green

Blue

SYNC_IN1

SYNC_IN2

DDC_OUT2

DDC_OUT1

VIDEO_1

VIDEO_2

VIDEO_3

SYNC_OUT1

SYNC_OUT2

GND

PWR_UP

PACVGA201

13

10

9

3

4

5

28

1

6

7

12

14

To Video

5 V

0.2 mF 0.2 mF

VF** − VIDEO EMI Filter

SF** − SYNC EMI Filter

15

16

0.2 mF

SD1

SD2

the PACVGA201 is in the power−down state. The value of this resistor should be chosen such that the extra charge deposited

repetition rate specified by the IEC−61000−4−2 standard is one pulse per second. When the PACVGA201 is in the power−up

state, an internal discharge resistor is connected to ground via a FET switch for this purpose.

components in the system to provide a discharge path to ground.