X5043/X5045

Characteristics subject to change without notice.

5 of 20

REV 1.1.2 5/29/01

www.xicor.com

SPI Serial Memory

The memory portion of the device is a CMOS Serial

EEPROM array with Xicor’s block lock protection. The

array is internally organized as x8 bits. The device fea-

tures a Serial Peripheral Interface (SPI) and software

protocol allowing operation on a simple four-wire bus.

cell, providing a minimum endurance of 1,000,000

cycles and a minimum data retention of 100 years.

The device is designed to interface directly with the

synchronous Serial Peripheral Interface (SPI) of many

popular microcontroller families.

The device contains an 8-bit instruction register that

controls the operation of the device. The instruction

code is written to the device via the SI input. There are

two write operations that requires only the instruction

byte. There are two read operations that use the

instruction byte to initiate the output of data. The

remainder of the operations require an instruction byte,

an 8-bit address, then data bytes. All instruction,

address and data bits are clocked by the SCK input. All

instructions (Table 1), addresses and data are trans-

ferred MSB first.

Clock and Data Timing

Data input on the SI line is latched on the first rising

edge of SCK after CS goes LOW. Data is output on the

SO line by the falling edge of SCK. SCK is static,

allowing the user to stop the clock and then start it

again to resume operations where left off. CS must be

LOW during the entire operation.

RESET pin

goes active?

DONE

Execute

Sequence

Execute

Sequence

Execute

Sequence

Error

≤ -Emax

-Emax < Error < Emax

YES

NO

Error

≥ Emax

Emax = Maximum Desired Error

- Error

=

- Error

=

Table 1. Instruction Set

Note:

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

Instruction Name

Instruction Format*

Operation

WREN

0000 0110

Set the Write Enable Latch (Enable Write Operations)

WRDI

0000 0100

Reset the Write Enable Latch (Disable Write Operations)

RSDR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register (Watchdog and Block Lock)

READ

Read Data from Memory Array Beginning at Selected Address

WRITE

Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)