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X5043M8I-2.7A Datasheet(PDF) 2 Page - Xicor Inc. |
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X5043M8I-2.7A Datasheet(HTML) 2 Page - Xicor Inc. |
2 / 20 page X5043/X5045 Characteristics subject to change without notice. 2 of 20 REV 1.1.2 5/29/01 www.xicor.com The memory portion of the device is a CMOS Serial EEPROM array with Xicor’s block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software proto- col allowing operation on a simple four-wire bus. The device utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the fall- ing edge of the clock input. Chip Select (CS) When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally. When WP is held high, all functions, including non vol- atile writes operate normally. WP going low while CS is still low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write. Reset (RESET, RESET) X5043/45, RESET/RESET is an active low/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A fall- ing edge of CS will reset the watchdog timer. PIN NAMES 8-Lead SOIC/PDIP/MSOP CS/WDI WP SO 1 2 3 4 RESET/RESET 8 7 6 5 VCC X5043/45 VSS SCK SI 14-Lead TSSOP CS NC SO 1 2 3 4 RESET/RESET 14 13 12 11 VCC X5043/45 NC NC NC WP NC 5 6 7 VSS NC 10 9 8 SCK SI Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage RESET/RESET Reset Output |
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