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WM8199 Datasheet(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8199 Datasheet(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 30 page  WM8199 Production Data w PD Rev 3.2 November 2003 9 INPUT VIDEO SAMPLING MCLK VSMP INPUT VIDEO t PER t VSMPSU t VSMPH t VSU t VH t RSU t RH t MCLKL t MCLKH Figure 3 Input Video Timing Note: 1. See Page 14 (Programmable VSMP Detect Circuit) for video sampling description. Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25 °C unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS MCLK period tPER 25 ns MCLK high period tMCLKH 11.3 14.1 ns MCLK low period tMCLKL 11.3 14.1 ns VSMP set-up time tVSMPSU 5 ns VSMP hold time tVSMPH 3 ns Video level set-up time tVSU 11 ns Video level hold time tVH 4 ns Reset level set-up time tRSU 11 ns Reset level hold time tRH 4 ns Notes: 1. tVSU and tRSU denote the set-up time required after the input video signal has settled. 2. Parameters are measured at 50% of the rising/falling edge. OUTPUT DATA TIMING MCLK OP[7:0] t PD Figure 4 Output Data Timing |
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