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TSEV8308500GLZA2 Datasheet(PDF) 4 Page - ATMEL Corporation |
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TSEV8308500GLZA2 Datasheet(HTML) 4 Page - ATMEL Corporation |
4 / 50 page 4 TS8308500 2193A–BDC–04/03 Electrical Operating Characteristics VEE = DVEE = -5V; VCC = +5V; VIN -VINB = 500 mVpp Full Scale differential input 50 Ω differentially terminated digital outputs Tj (typical) = 70 °C Table 3. Electrical Specifications Parameter Symbol Test Level Value Unit Note Min Typ Max Power Requirements Positive supply voltage Analog Digital (ECL) Digital (LVDS) V CC V PLUSD VPLUSD 1 4 4 4.5 – 1.4 5 0 2.4 5.5 – 2.6 V V V Positive supply current Analog Digital ICC I PLUSD 1 1 – – 420 130 445 145 mA mA Negative supply voltage VEE 1 -5.5 -5 -4.5 V Negative supply current Analog Digital AI EE DI EE 1 1 – – 185 160 200 180 mA mA Nominal power dissipation PD 1 – 3.9 4.1 W Power supply rejection ratio PSRR 4 – 0.5 2 mW Resolution –– – – 8 bits (2) Analog Inputs Full-scale input voltage range (differential mode) (0V common mode voltage) V IN V INB 4 – -125 -125 – – 125 125 mV mV Full-scale input voltage range (single-ended input option) (14) V IN V INB 4 – -250 – – 0 250 – mV mV Analog input capacitance C IN 4– 3 3.5 pF Input bias current I IN 4 – 10 20 µA Input Resistance R IN 40.5 1 – M Ω Full Power input Bandwidth (-3 dB) FPBW 4 – 1.8 – GHz Small signal input Bandwidth (10% full-scale) SSBW 4 – 1.7 – GHz Clock Inputs Logic compatibility for clock inputs (14) –– ECL or specified clock input power level in dBm – (8) ECL Clock inputs voltages (V CLK or VCLKB): – 4 – – – – Logic 0 voltage VIL –– – -1.5 V Logic 1 voltage V IH –-1.1 – – V Logic 0 current I IL –– 5 50 µA Logic 1 current IIH –– 5 50 µA Clock input power level into 50 Ω termination – – dBm into 50 Ω – |
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