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TSEV8308500GLZA2 Datasheet(PDF) 2 Page - ATMEL Corporation |
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TSEV8308500GLZA2 Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 50 page 2 TS8308500 2193A–BDC–04/03 Functional Description Block Diagram Figure 1. Simplified Block Diagram Functional Description The TS8308500 is an 8-bit 500 Msps ADC based on an advanced high-speed bipolar technol- ogy featuring a cutoff frequency of 25 GHz. The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry. Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a resynchronization stage followed by 75 Ω differential output buffers. The TS8308500 works in fully differential mode from analog inputs up to digital outputs. The TS8308500 features a full-power input bandwidth of 1.3 GHz. Control pin GORB is provided to select either the Gray or Binary data output format. The gain control pin is provided in order to adjust the ADC gain. A Data Ready output asynchronous reset (DRRB) is available on TS8308500. The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated poly- silicon resistors, which allow enhanced radiation tolerance (no performance drift measured at 150 kRad total dose). Master/Slave Track & Hold Amplifier VIN, VINB Clock Buffer GAIN GORB DATA, DATAB OR, ORB DRRB DR, DRB CLK, CLKB 4 4 5 4 5 8 8 Resistor Chain Analog Encoding Block Interpolation Stages Regeneration Latches Error Correction & Decode Logic Output Latches & Buffers |
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