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TC90A49P Datasheet(PDF) 8 Page - Toshiba Semiconductor |
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TC90A49P Datasheet(HTML) 8 Page - Toshiba Semiconductor |
8 / 17 page TC90A49P/F 2001-03-06 8/17 Vertical edge enhancement characteristic (Zoom) 7. PLL 8 × multiplier circuit Multiplies by eight the input subcarrier signal which is locked to the frequency of burst signal to generate 8 fsc and 4 fsc system clocks. 8. DA converter (DAC) The Y / C signal separated using the 4 fsc clock as the basic clock is over-sampled by the 8 fsc clock, then DA-converted. |
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