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PADS122U04IPWR Datasheet(PDF) 9 Page - Texas Instruments |
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PADS122U04IPWR Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 67 page  Synchronization word RESET command RESET RX Synchronization word New command ttd(RSRX)t tw(RSL) RX/TX VIH VIL tr(RX) ttBAUDt tf(RX) ttBAUDt tJITTER tJITTER 9 ADS122U04 www.ti.com SBAS752 – MAY 2017 Product Folder Links: ADS122U04 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) The UART baud rate affects the command latch timing; see the Command Latching section for more details. (2) See the Timeout section for more information. tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz (normal mode) and 512 kHz (turbo mode). 7.6 UART Timing Requirements over operating ambient temperature range and DVDD = 2.3 V to 5.5 V (unless otherwise noted) MIN TYP MAX UNIT 1/tBAUD Bus baud rate 2 120 kBaud tr(RX) Rise time 10-pF load 15 % of tBAUD tf(RX) Fall time 10-pF load 15 % of tBAUD tJITTER Edge timing variance –1% 1% tw(RSL) Pulse duration, RESET low 250 ns td(RSRX) Delay time, start of communication after RESET rising edge (or RESET command decoded(1)) TBD ns Timeout(2) Normal mode 32760 tMOD Turbo mode 65520 (1) tCLK = 1 / fCLK. Oscillator frequency fCLK = 1.024 MHz (normal mode) and 2.048 MHz (turbo mode). tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz (normal mode) and 512 kHz (turbo mode). (2) The UART baud rate affects the command latch timing; see the Command Latching section for more details. 7.7 UART Switching Characteristics over operating ambient temperature range and DVDD = 2.3 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT(1) tpd(RDDR) Propagation delay time, RDATA command decoded to DRDY rising edge(2) Manual data read mode TBD tCLK tpd(RDTX) Propagation delay time, RDATA command decoded to TX falling edge(2) Manual data read mode 2 tBAUD tpd(DRTX) Propagation delay time, DRDY rising edge to TX falling edge(2) Automatic data read mode 2 tBAUD tw(DRH) Pulse duration, DRDY high 2 tMOD tw(DRL) Pulse duration, DRDY low Automatic data read mode 4 tCLK tp(RREG) Propagation delay time, RREG command decoded to TX falling edge(2) 2 tBAUD tp(GPIO) Propagation delay time, WREG command decoded to GPIOx output valid(2) TBD TBD ns Figure 1. UART Timing Requirements Figure 2. RESET Pin and RESET Command Timing Requirements |
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