DVIULC6-4SC6Y

Technical information

Doc ID 018878 Rev 2

7/12

3.3

How to ensure good ESD protection

While the DVIULC6-4SC6Y provides a high immunity to ESD surge, an efficient protection

depends on the layout of the board. In the same way, with the rail to rail topology, the track

possible to avoid over voltages due to parasitic phenomena (see Figure 13 and Figure 14 for

layout considerations).

Figure 13.

IESD behavior: parasitic phenomena due to unsuitable layout

Figure 14.

ESD behavior: layout optimization and addition of a 100 nF capacitor

Lw

VI/O

ESD

SURGE

GND

I/O

Lw di

dt

Lw di

dt

V+ =

CL

V

+V +Lw

BUS

F

di

dt

surge >0

di

dt

surge <0

V- =

CL

-V -Lw

F

t

tr=1ns

VV

CC

F

+

Lw

di

dt

POSITIVE

SURGE

183V

-Lw

di

dt

t

tr=1ns

-

NEGATIVE

SURGE

-178V

REF1=GND

VI/O

ESD

SURGE

I/O

REF2=+

C=100nF

Lw

V+

V

CL

CC

F

V+

=

surge >0

surge <0

VV

CL

F

-

- =

t

V+

CL

POSITIVE

SURGE

t

V-

CL

NEGATIVE

SURGE