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72605L25PF Datasheet(PDF) 5 Page - Integrated Device Technology |
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72605L25PF Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 17 page  5 IDT72605/72615 CMOS SYNCBiFIFO™ 256 x 18x 2 and 512 x 18 x 2 INDUSTRIALTEMPERATURERANGE AC ELECTRICAL CHARACTERISTICS (Industrial: VCC = 5V ± 10%, TA = -40 °C to +85°C) +5V 1.1K Ω 680 Ω 30pF* D.U.T. 2704 drw 04 Industrial IDT72615L20 IDT72615L25 IDT72615L35 IDT72615L50 IDT72605L20 IDT72605L25 IDT72605L35 IDT72605L50 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Timing Figures fCLK Clockfrequency — 50 — 40 — 28 — 20 MHz — tCLK Clock cycle time 20 — 25 — 35 — 50 — ns 4,5,6,7 tCLKH Clock HIGH time 8 — 10 — 14 — 20 — ns 4,5,6,7,12,13,14,15 tCLKL Clock LOW time 8 — 10 — 14 — 20 — ns 4,5,6,7,12,13,14,15 tRS Resetpulsewidth 20 — 25 — 35 — 50 — ns 3 tRSS Resetsetuptime 12 — 15 — 21 — 30 — ns 3 tRSR Reset recovery time 12 — 15 — 21 — 30 — ns 3 tRSF Resettoflagsininitialstate — 27 — 28 — 35 — 50 ns 3 tA Dataaccesstime 3 10 3 15 3 21 3 25 ns 5,7,8,9,10,11 tCS Controlsignalsetuptime(1) 6 — 6 — 8 — 10 — ns 4,5,6,7,8,9,10,11, 12,13,14,15 tCH Controlsignalholdtime(1) 1 — 1 — 1 — 1 — ns 4,5,6,7,10,11,12, 13,14,15 tDS Datasetuptime 6 — 6 — 8 — 10 — ns 4,6,8,9,10,11 tDH Dataholdtime 1 — 1 — 1 — 1 — ns 4,6 tOE OutputEnableLOWtooutputdatavalid(2) 3 10 3 13 3 20 3 28 ns 5,7,8,9,10,11 tOLZ OutputEnableLOWtodatabusatLow-Z(2) 0 — 0 — 0 — 0 — ns 5,7,8,9,10,11 tOHZ Output Enable HIGH to data bus at High-Z(2) 3 10 3 13 3 20 3 28 ns 5,7,10,11 tFF Clock to Full Flag time — 10 — 15 — 21 — 30 ns 4,6,10,11 tEF Clock to Empty Flag time — 10 — 15 — 21 — 30 ns 5,7,8,9,10,11 tPAE ClocktoProgrammable — 12 — 15 — 21 — 30 ns 12,14 Almost-EmptyFlagtime tPAF ClocktoProgrammable — 12 — 15 — 21 — 30 ns 13,15 Almost-FullFlagtime tSKEW1 Skew between CLKA & CLKB 10 — 12 — 17 — 20 — ns 4,5,6,7,8,9,10,11 forEmpty/FullFlags(2) tSKEW2 Skew between CLKA & CLKB 17 — 19 — 25 — 34 — ns 4,7,12,13,14,15 forProgrammableFlags(2) NOTES: 1. Control signals refer to CSA, R/WA, ENA, A2, A1, A0, R/WB, ENB. 2. Minimum values are guaranteed by design. AC TEST CONDITIONS In Pulse Levels GND to 3.0V InputRise/FallTimes 3ns InputTimingReferenceLevels 1.5V OutputReferenceLevels 1.5V OutputLoad See Figure 2 orequivalentcircuit Figure 2. Output Load * Includes jig and scope capacitances. |
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