8

INDUSTRIALTEMPERATURERANGE

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

outofbusandisreadfromoutputregisterintothree-statebuffer.Inbypassmode,

→Aoutputregister.

→Boutputregister.

Refertopindescriptionsformoreinformation.

TABLE 3 ⎯ FLAG OFFSET REGISTER FORMAT

NOTE:

1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.

17

16

15

14

13

12

11

10

9876543210

Register

XXXXXXXXX

A

→B FIFO Almost-Empty Flag Offset

17

16

15

14

13

12

11

10

9876543210

XXXXXXXXX

A

→B FIFO Almost-Full Flag Offset

17

16

15

14

13

12

11

10

9876543210

Register

XXXXXXXXX

B

→A FIFO Almost-Empty Flag Offset

17

16

15

14

13

12

11

10

9876543210

XXXXXXXXX

B

→A FIFO Almost-Full Flag Offset

TABLE 4 ⎯ INTERNAL FLAG TRUTH TABLE

Number of Words

in FIFO

From

To

EF

PAE

PAF

FF

0

0

LOW

LOW

HIGH

HIGH

1

n

HIGH

LOW

HIGH

HIGH

n+1

D-(m+1)

HIGH

HIGH

HIGH

HIGH

D-m

D-1

HIGH

HIGH

LOW

HIGH

D

D

HIGH

HIGH

LOW

LOW

NOTE:

D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)

TABLE 5 ⎯ PORT B OPERATION CONTROL SIGNALS

Data B

I/O

Port B Operation

000

I

Data B is written on CLKB

↑. This write cycle immediately following output low-impedance cycle is prohibited. Note

impedance state.

0

0

1

I

Data B is written on CLKB

↑.

0

1

X

I

Data B is ignored

1

0

0

O

≠ Data B is low-impedance

1

0

1

O

≠, Data B is high- impedance

1

1

0

O

1

1

1

O

NOTES:

bypass data is read from the Port B output register.

→B read pointer does not advance.