256 x 18 x 2

512 x 18 x 2

IDT72605

IDT72615

1

©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

DSC-2704/10

FEBRUARY 2013

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

transfers

of the data bus

to-A FIFO

Quad Flatpack) and 68-pin PLCC

°°°°°C to +85°°°°°C)

DESCRIPTION:

The IDT72605 and IDT72615 are very high-speed, low-power bidirec-

tionalFirst-In,First-Out(FIFO)memories,withsynchronousinterfaceforfast

read and write cycle times. The SyncBiFIFO™ is a data buffer that can store

orretrieveinformationfromtwosourcessimultaneously.TwoDual-PortFIFO

memory arrays are contained in the SyncBiFIFO; one data buffer for each

direction.

The SyncBiFIFO has registers on all inputs and outputs. Data is only

transferred into the I/O registers on clock edges, hence the interfaces are

synchronous. EachPorthasitsownindependentclock.Datatransferstothe

I/O registers are gated by the enable signals. The transfer direction for each

portiscontrolledindependentlybyaread/writesignal. Individualoutputenable

signals control whether the SyncBiFIFO is driving the data lines of a port or

whether those data lines are in a high-impedance state.

Bypass control allows data to be directly transferred from input to output

registerineitherdirection.

TheSyncBiFIFOhaseightflags.TheflagpinsareFull,Empty,Almost-Full,

andAlmost-EmptyforbothFIFOmemories.TheoffsetdepthsoftheAlmost-Full

andAlmost-Emptyflagscanbeprogrammedtoanylocation.

TheSyncBiFIFOisfabricatedusinghigh-speed,submicronCMOStech-

nology.

FLAG

LOGIC

MEMORY

ARRAY

512 x 18

256 x 18

INPUT REGISTER

MUX

OUTPUT REGISTER

HIGH

Z

CONTROL

OUTPUT REGISTER

INPUT REGISTER

MUX

MEMORY

ARRAY

512 x 18

256 x 18

HIGH

Z

CONTROL

FLAG

LOGIC

RESET

LOGIC

POWER

SUPPLY

R/

R/

RS

GND

3

μP

INTERFACE

7

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