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72291L15PFG Datasheet(PDF) 2 Page - Integrated Device Technology |
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72291L15PFG Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 26 page  COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 2 TQFP (PN64-1, ORDER CODE: PF) STQFP (PP64-1, ORDER CODE: TF) TOP VIEW DESCRIPTION (CONTINUED) PIN 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 WEN SEN DC(1) VCC VCC GND(2) GND(2) GND(2) GND(2) GND(2) GND(2) GND(2) GND(2) GND(2) D8 D7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DNC(3) DNC(3) GND DNC(3) DNC(3) VCC DNC(3) DNC(3) DNC(3) GND DNC(3) DNC(3) Q8 Q7 Q6 GND 4675 drw 02 TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable (WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen WEN is asserted. The output port is controlled by a Read Clock (RCLK) input andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-statecontroloftheoutputs. The frequencies of both the RCLK and the WCLK signals may vary from 0 tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency of the one clock input with respect to the other. Therearetwopossibletimingmodesofoperationwiththesedevices:IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread operation,whichconsistsofactivatingRENandenablingarisingRCLKedge, willshiftthewordfrominternalmemorytothedataoutputlines. InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectlyto thedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoesnot havetobeassertedforaccessingthefirstword.However,subsequentwords writtentotheFIFOdorequireaLOWonRENforaccess. ThestateoftheFWFT/ SIinputduringMasterResetdeterminesthetimingmodeinuse. ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan provide, the FWFT timing mode permits depth expansion by chaining FIFOs inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding data inputs of the next). No external logic is required. TheseFIFOshavefiveflagpins,EF/OR(EmptyFlagorOutputReady),FF/ IR(FullFlagorInputReady),HF(Half-fullFlag),PAE(ProgrammableAlmost- Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFFfunctions are selected in IDT Standard mode. The IR andORfunctionsareselectedin NOTES: 1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open. 2. This pin may either be tied to GND or left open. 3. DNC = Do Not Connect. PIN CONFIGURATIONS |
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