 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DT72281 Datasheet(PDF) 1 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
DT72281 Datasheet(HTML) 1 Page - Integrated Device Technology |
|
|
1 / 26 page  1 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4675/5 © MARCH 2013 IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES CMOS SuperSync FIFO™ 65,536 x 9 131,072 x 9 IDT72281 IDT72291 FEATURES: ••••• Choose among the following memory organizations: IDT72281 65,536 x 9 IDT72291 131,072 x 9 ••••• Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs ••••• 10ns read/write cycle time (6.5ns access time) ••••• Fixed, low first word data latency time ••••• Auto power down minimizes standby power consumption ••••• Master Reset clears entire FIFO ••••• Partial Reset clears data, but retains programmable settings ••••• Retransmit operation with fixed, low first word data latency time ••••• Empty, Full and Half-Full flags signal FIFO status ••••• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets ••••• Program partial flags by either serial or parallel means ••••• Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) ••••• Output enable puts data outputs into high impedance state ••••• Easily expandable in depth and width ••••• Independent Read and Write clocks (permit reading and writing simultaneously) ••••• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64- pin Slim Thin Quad Flat Pack (STQFP) ••••• High-performance submicron CMOS technology ••••• Industrial temperature range (-40°C to +85°C) is available DESCRIPTION: TheIDT72281/72291areexceptionallydeep,highspeed,CMOSFirst-In- First-Out(FIFO)memorieswithclockedreadandwritecontrols. TheseFIFOs offernumerousimprovementsoverpreviousSuperSyncFIFOs,includingthe following: ••••• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. ••••• The period required by the retransmit operation is now fixed and short. ••••• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable clock cycle counting delay associated with the latency period found on previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.) SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom- munications,datacommunicationsandotherapplicationsthatneedtobuffer largeamountsofdata. INPUT REGISTER OUTPUT REGISTER RAM ARRAY 65,536 x 9 131,072 x 9 FLAG LOGIC FF/IR PAF EF/OR PAE HF READ CONTROL LOGIC WRITE CONTROL LOGIC RESET LOGIC WEN WCLK D0 -D8 LD MRS REN RCLK OE Q0 -Q8 OFFSET REGISTER PRS FWFT/SI SEN RT 4675 drw01 WRITE POINTER READ POINTER FUNCTIONAL BLOCK DIAGRAM |
Similar Part No. - DT72281_13 |
|
Similar Description - DT72281_13 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
