CM1236

http://onsemi.com

2

Figure 1. Block Diagram

ESD Protection Architecture

Conceptually, an ESD protection device performs the

following actions upon an ESD strike discharge into a

protected ASIC (see Figure 2):

1. When an ESD potential is applied to the system

under test (contact or air−discharge), Kirchoff’s

Current Law (KCL) dictates that the Electrical

Overstress (EOS) currents will immediately divide

throughout the circuit, based on the dynamic

impedance of each path.

2. Ideally, the classic shunt ESD clamp will switch

within 1 ns to a low−impedance path and return

the majority of the EOS current to the chassis

shield/reference ground. In actuality, if the ESD

than the ASIC it is protecting, or if the Dynamic

lower than the ASIC’s I/O cell circuitry, then the

ASIC will have to absorb a large amount of the

EOS energy, and be more likely to fail.

3. Subsequent to the ESD/EOS event, both devices

must immediately return to their original

specifications, and be ready for an additional

strike. Any deterioration in parasitics or clamping

capability should be considered a failure, since it

can then affect signal integrity or subsequent

protection capability. (This is known as

“multi−strike” capability.)

In the CM1236 architecture, the signal line leading the

connector to the ASIC routes through the CM1236 chip

which provides 100

W matched differential channel

characteristic impedance that helps optimize 100

W load

impedance applications such as the HDMI high speed data

lines.

NOTE: When each of the channels are used individually

for single−ended signal lines protection, the

individual channel provides 50

W characteristic

impedance matching.

The load impedance matching feature of the CM1236

helps to simplify system designer’s PCB layout

considerations in impedance matching and also eliminates

associated passive components.

The route through the architecture enables the CM1236 to

provide matched impedance for the signal path between the

connector and the ASIC. Besides this function, this circuit

arrangement also changes the way the parasitic inductance

interacts with the ESD protection circuit and helps reduce

Figure 2. Standard ESD Protection Device Block

Diagram