Detailed Description

The MAX1169 ADC uses successive-approximation

conversion (SAR) techniques and on-chip track-and-

hold (T/H) circuitry to capture and convert an analog

signal to a serial 16-bit digital output.

The MAX1169 performs a unipolar conversion on its

single analog input using its internal 4MHz clock. The

full-scale analog input range is determined by the inter-

nal reference or by an externally applied reference volt-

The flexible 2-wire serial interface provides easy con-

nection to microcontrollers (µCs) and supports data

rates up to 1.7MHz. Figure 3 shows the simplified func-

tional diagram for the MAX1169 and Figure 4 shows the

typical application circuit.

Power Supply

To maintain a low-noise environment, the MAX1169

provides separate analog and digital power-supply

inputs. The analog circuitry requires a +5V supply and

consumes only 900µA at sampling rates up to

58.6ksps. The digital supply voltage accepts voltages

from +2.7V to +5.5V to ensure compatibility with low-

voltage ASICs. The MAX1169 wakes up in shutdown

Analog Input and Track/Hold

The MAX1169 analog input contains a T/H capacitor,

T/H switches, comparator, and a switched capacitor

digital-to-analog converter (DAC) (Figure 5).

As shown in Figure 11c, the MAX1169 acquisition peri-

od is the two clock cycles prior to the conversion peri-

od. The T/H switches are normally in the hold position.

During the acquisition period, the T/H switches are in

signal. Before a conversion begins, the T/H switches

as a sample of the analog input signal.

During the conversion interval, the switched capacitive

DAC adjusts to restore the comparator input voltage to

zero within the limits of 16-bit resolution. This is equiva-

lent to transferring a charge of 35pF

forming a digital representation of the analog input sig-

nal. During the conversion period, the MAX1169 holds

SCL low (clock stretching).

58.6ksps, 16-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

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Pin Description

PIN

NAME

FUNCTION

1

DGND

Digital Ground

2

SCL

Clock Input

3

SDA

Data Input/Output

4

ADD2

Address Select Input 2

5

ADD1

Address Select Input 1

6

ADD0

Address Select Input 0

Digital Power Input. Bypass to DGND with a 0.1µF capacitor.

Analog Power Input. Bypass to AGND with a 0.1µF capacitor.

9

AGND

Analog Ground

10

AIN

Analog Input

11

AGNDS

Analog Signal Ground. Negative reference for analog input. Connect to AGND.

12

REFADJ

Internal Reference Output and Reference Buffer Input. Bypass to AGND with a 0.1µF capacitor.

13

REF

Reference Buffer Output and External Reference Input. Bypass to AGND with a 10µF capacitor

when using the internal reference.

14

ADD3

Address Select Input 3