DDR SDRAM

1GB, 2GB Registered DIMM

Rev. 1.1 August. 2003

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Ordering Information

Operating Frequencies

Part Number

Density

Organization

Component Composition

Height

M312L2923BG0-CB3/A2/B0

1GB

128M x 72

64Mx8( K4H510838B) * 18EA

1,125mil

M312L2920BG0-CB3/A2/B0

1GB

128M x 72

128Mx4( K4H510438B) * 18EA

1,125mil

M312L5720BG0-CB3/A2/B0

2GB

256M x 72

128Mx4( K4H510438B) * 36EA

1,200mil

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

Speed @CL2

133MHz

133MHz

100MHz

Speed @CL2.5

166MHz

133MHz

133MHz

CL-tRCD-tRP

2.5-3-3

2-3-3

2.5-3-3

Feature

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

184Pin Registered DIMM based on 512Mb B-die FBGA (x4, x8)