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LTC3900 Datasheet(PDF) 8 Page - Linear Technology

Part # LTC3900
Description  Synchronous Rectifier Driver for Forward Converters
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC3900 Datasheet(HTML) 8 Page - Linear Technology

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LTC3900
8
3900i
APPLICATIO S I FOR ATIO
Figure 3. Timer Circuit
ZTMR
RTMR
CTMR
7
3900 F03
TMR
4
R1
R2
VCC
TIMEOUT
TIMER
RESET
SYNC
FG
CG
TIMER RESET
(INTERNAL)
TIMER
SG
TIMEOUT
THRESHOLD
LAST
PULSE
3900 F04
A typical forward converter cycle always turns on Q3 and
Q4 alternately and the SYNC input should alternate be-
tween positive and negative pulses. The LTC3900 timer
also includes sequential logic to monitor the SYNC input
sequence. If after one negative pulse, the SYNC compara-
tor receives another negative pulse, the LTC3900 will not
reset the timer cap. If no positive SYNC pulse appears,
both drivers are shut off once the timer times out. Once
positive pulses reappear the timer resets and the drivers
start switching again. This is to protect the external
components in situations where only negative SYNC pulse
is present and FG output remains high. Figure 5 shows the
timer waveforms with incorrect SYNC pulses.
The LTC3900 has two separate SYNC comparators (S+
and Sin the Block Diagram) to detect the positive and
negative pulses. The threshold voltages of both compara-
tors are designed to be of the same magnitude (1.4V
typical) but opposite in polarity. In some situations, for
example during power up or power down, the SYNC pulse
magnitude may be low, slightly higher or lower than the
threshold of the comparators. This can cause only one of
the SYNC comparators to trip. This also appears as
incorrect SYNC pulse and the timer will not reset.
The timeout period is determined by the external RTMR and
CTMR values and is independent of the VCC voltage. This is
achieved by making the timeout threshold a ratio of VCC.
The ratio is 0.2x, set internally by R1 and R2 (see Figure 3).
The timeout period should be programmed to be around
1 period of the primary switching frequency using the
following formula:
TIMEOUT = 0.2 • RTMR • CTMR + 0.27E-6
To reduce error in the timeout setting due to the discharge
time, select CTMR between 100pF and 1000pF. Start with
a CTMR around 470pF and then calculate the required
RTMR. CTMR should be placed as close as possible to the
LTC3900 with minimum PCB trace between CTMR, the
TIMER pin and GND. This is to reduce any ringing caused
by the PCB trace inductance when CTMR discharges. This
ringing may introduce error to the timeout setting.
The timer input also includes a current sinking clamp
circuit (ZTMR in Figure 3) that clamps this pin to about
0.5 • VCC if there is missing SYNC/timer reset pulse. This
clamp circuit prevents the timer cap from getting fully
charged up to the rail, which results in a longer discharge
time. The current sinking capability of the circuit is around
1mA. The timeout function can be disabled by connecting
the timer pin to GND.
Figure 4. Timer Waveforms
SYNC
FG
CG
TIMER RESET
(INTERNAL)
TIMER
TIMEOUT
THRESHOLD
3900 F05
TIMEOUT
MISSING/LOW
POSITIVE
SYNC PULSE
TIMER RESET AFTER
RECEIVING POSITIVE
SYNC PULSE
TIMER DO NOT RESET
AT SECOND NEGATIVE
SYNC PULSE
Figure 5. Timer Waveforms with Incorrect SYNC Pulses


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