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A8580 Datasheet(PDF) 8 Page - Allegro MicroSystems |
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A8580 Datasheet(HTML) 8 Page - Allegro MicroSystems |
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8 / 41 page  Wide Input Voltage, 2.4 MHz, 2.5 AAsynchronous Buck Regulator With Low-IQ Standby, Sleep Mode, External Synchronization, and NPOR Output A8580 7 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Characteristic Symbol Test Conditions Min. Typ. Max. Unit Error Amplifier Feedback Input Bias Current2 IFB –38 – –16 nA Open Loop Voltage Gain AVOL VCOMP = 1.2 V – 65 – dB Transconductance gm 400 mV < VFB 550 750 950 μA/V 0 V < VFB < 400 mV 275 375 475 μA/V Output Current IEA VCOMP = 1.2 V – ±75 – μA COMP Pull-Down Resistance RCOMP FAULT = 1 or HICCUP = 1 – 1 – KΩ Pulse Width Modulation (PWM) PWM Ramp Offset PWMOFFS VCOMP level required for 0% duty cycle – 400 – mV Minimum Controllable PWM On-Time tON(MIN)PWM 12 V < VIN < 16 V, IOUT = 1 A, VBOOT – VSW = 4.5 V – 95 135 ns Minimum Switch Off-Time tOFF(MIN)PWM – 95 130 ns COMP to SW Current Gain gmPOWER – 2.85 – A/V Slope Compensation3 SE fOSC = 2.44 MHz 2.1 3.0 3.9 A/μs fOSC = 1.00 MHz 0.60 0.91 1.2 A/μs fOSC = 252 kHz 0.14 0.20 0.26 A/μs MOSFET Parameters1 High-Side MOSFET On-Resistance5 RDS(on)HS TJ =25ºC, VBOOT – VSW = 4.5 V, IDS = 0.4 A – 110 125 mΩ TJ =150ºC, VBOOT – VSW = 4.5 V, IDS = 0.4 A – 190 215 mΩ High-Side MOSFET Leakage2,6 Ilkg(HS) TJ < 85°C, VSLEEPn ≤ 0.5 V, VSW = 0 V, VIN = 16 V – – 10 µA TJ ≤ 150°C, VSLEEPn ≤ 0.5 V, VSW = 0 V, VIN = 16 V – 60 150 µA SW Node Slew Rate3 SRSW 12 V < VIN < 16 V – 0.72 – V/ns Low-Side MOSFET On-Resistance5 RDS(on)LS TJ = 25ºC, VIN ≥ 6 V, IDS = 0.1 A – – 10 Ω PWM Switching Frequency Base PWM Switching Frequency fOSC RFSET = 8.06 kΩ, VPWM/PFMn= high 2.20 2.44 2.70 MHz RFSET = 23.7 kΩ, VPWM/PFMn= high 0.90 1.00 1.10 MHz RFSET = 102 kΩ, VPWM/PFMn= high – 252 – kHz PWM Synchronization Timing Synchronization Frequency Range fSYNC(MULT) 1.2 × fOSC(typ) – 1.5 × fOSC(typ) − Synchronized PWM Frequency fSYNC(PWM) – – 2.9 MHz Synchronization Input Duty Cycle DSYNC – – 80 % Synchronization Input Pulse Width twSYNC 200 – – ns Synchronization Input Rise Time3 trSYNC – 10 15 ns Synchronization Input Fall Time3 tfSYNC – 10 15 ns Continued on the next page… ELECTRICAL CHARACTERISTICS (continued): valid at 4.0 V ≤ VIN ≤ 35 V, –40°C ≤ TA = TJ ≤ 150°C; unless otherwise speci- fied |
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