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A4411KLVTR-T Datasheet(PDF) 2 Page - Allegro MicroSystems |
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A4411KLVTR-T Datasheet(HTML) 2 Page - Allegro MicroSystems |
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2 / 45 page  Adjustable Frequency Buck or Buck-Boost Pre-Regulator with a Synchronous Buck, 3 LDOs, Pulse-Width Window Watchdog, NPOR, and POK5V A4411 2 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com SELECTION GUIDE Part Number Temperature Range Package Packing1 Lead Frame A4411KLVTR-T –40 to 135°C 38-pin eTSSOP with thermal pad 4000 pieces per 7-inch reel 100% matte tin 1 Contact Allegro for additional packing options. • High-voltage ignition enable input (ENBAT) • ENBAT status indicator output (ENBATS) • SLEW rate control pin helps reduce EMI/EMC • Frequency dithering helps reduce EMI/EMC • OV and UV protection for all four CPU supply rails • Pin-to-pin and pin-to-ground tolerant at every pin • Thermal shutdown protection • −40°C to 150°C junction temperature range Protectionfeaturesincludeunder-andovervoltagelockoutonallfour CPU supply rails. In case of a shorted output, all linear regulators feature foldback overcurrent protection. In addition, the V5P output is protected from a short-to-battery event. Both switching regulators include pulse-by-pulse current limit, hiccup mode short-circuit protection,LXshort-circuitprotection,missingasynchronousdiode protection (VREG only), and thermal shutdown. The A4411 is supplied in a low-profile 38-lead eTSSOP package (suffix “LV”) with exposed power pad. FEATURES AND BENEFITS (continued) DESCRIPTION (continued) Table of Contents Features and Benefits 1 Description 1 Applications 1 Package 1 Simplified Block Diagram 1 Selection Guide 2 Specifications 3 Absolute Maximum Ratings 3 Thermal Characteristics 3 Functional Block Diagrams 4 Pinout Diagram and Terminal List Table 7 Electrical Characteristics 8 Adjustable Synchronous Buck Regulator 11 Linear Regulator (LDO) 13 Control Inputs 14 Diagnostic Outputs 15 Pulse Width Window Watchdog Timer (PWWD) 17 Functional Description 18 Overview 18 Buck-Boost Pre-Regulator (VREG) 18 Adjustable Synchronous Buck Regulator (ADJ) 18 Low Dropout Regulators (LDOs) 19 Tracking Input (TRACK) 19 Pulse-Width Window Watchdog (PWWD) 20 Dual Bandgaps (BGVREF, BGFAULT) 21 Adj. Frequency and Synchronization (FSET/SYNC) 21 Frequency Dithering and LX1 Slew Rate Control 21 Enable Inputs (ENB, ENBAT) 22 Bias Supply (VCC) 22 Charge Pump (VCP, CP1, CP2) 22 Startup and Shutdown Sequences 22 Fault Reporting (NPOR, POK5V) 22 Timing Diagrams 26 Design and Component Selection 33 PWM Switching Frequency (RFSET) 33 Charge Pump Capacitors 33 Pre-Regulator Output Inductor (L1) 33 Pre-Regulator Output Capacitance 33 Pre-Regulator Ceramic Input Capacitance 34 Pre-Regulator Asynchronous Diode (D1) 34 Pre-Regulator Boost MOSFET (Q1) 34 Pre-Regulator Boost Diode (D2) 34 Pre-Regulator Soft-Start and Hiccup Timing (CSS1)34 Pre-Regulator Compensation (RZ1, CZ1, CP1) 35 Synchronous Buck Component Selection 36 Setting the Output Voltage (RFB1 and RFB2) 36 Synchronous Buck Output Inductor (L2) 36 Synchronous Buck Output Capacitance 37 Synchronous Buck Compensation (RZ2, CZ2, CP2) 37 Synchronous Buck Soft-Start and Hiccup Timing 38 Linear Regulators 38 Internal Bias (VCC) 38 Signal Pins (NPOR, POK5V, WDOUT, ENBATS) 38 PCB Layout Recommendations 39 Package Outline Drawing 44 |
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