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A4410KLVTR-T Datasheet(PDF) 6 Page - Allegro MicroSystems

Part # A4410KLVTR-T
Description  Programmable watchdog timer with a 30 ms activation delay
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A4410KLVTR-T Datasheet(HTML) 6 Page - Allegro MicroSystems

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Adjustable Frequency Buck or Buck/Boost Pre-Regulator with a
Synchronous Buck, 3 Internal LDOs, Window Watchdog Timer, and NPOR
A4410
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
Number
Name
Function
1
VCP
Charge pump reservoir capacitor
2,3
VIN
Input voltage
4,9
GND
Ground
5
N/C
No Connect
6
VCC
Internal voltage regulator bypass capacitor pin
7
SS1
Soft start programming pin for the buck/boost pre-regulator
8
COMP1
Error amplifier compensation network pin for the buck/boost pre-regulator
10
TRACK
Tracking control: Open/High – V5P tracks 3V3, GND/Low – V5P tracks
V5
11
NPOR
Active LOW, open-drain regulator fault detection output
12
POK5V
PowerOK output indicating when either the V5 or V5P rail is under-
voltage (UV)
13
ENBAT1S Open drain ignition status output, for ENBAT1 only
14
ENBAT2S Open drain ignition status output, for ENBAT2 only
15
FSET/
SYNC
Frequency setting and synchronization input
16
ENBAT1
Ignition enable input from the key/switch via a 1K of resistance
17
ENBAT2
Ignition enable input from the key/switch via a 1K of resistance
18
ENB
Logic enable input from the micro-controller
19
3V3
3.3 V regulator output
20
WDIN
Watchdog refresh input (rising edge triggered) from a micro-controller or
DSP
21
WDADJ
The watchdog wait/delay time is programmed by connecting RADJ from
this pin to ground
22
WDENn
Watchdog enable pin: Open/Low – WD is enabled, High – WD is disabled
23
V5P
5 V tracking/protected regulator output
24
SS2
Soft start programming pin for the 1.25 V synchronous buck
25
FB1V25
Feedback pin for the 1.25 V regulator
26
COMP2
Error amplifier compensation network pin for the 1.25 V synchronous
regulator
27,28
PGND
Power ground for the 1.25 V synchronous regulator / gate driver
29,30
LX2
Switching node for the 1.25 V synchronous regulator
31
V5
5 V regulator output
32
VREG
Output of the buck-boost and input for the LDOs and 1.25 VOUT sync.
Buck
33
LG
Boost gate drive output for the buck/boost pre-regulator
34
SLEW
Slew rate adjustment for the rise time of LX1
35,36
LX1
Switching node for the buck/boost pre-regulator
37
CP1
Charge pump capacitor connection
38
CP2
Charge pump capacitor connection
PAD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
PAD
VCP
VIN
VIN
GND
N/C
VCC
SS1
COMP1
GND
TRACK
NPOR
POK5V
ENBAT1S
ENBAT2S
FSET/SYNC
ENBAT1
ENBAT2
ENB
3V3
CP2
CP1
LX1
LX1
SLEW
LG
VREG
V5
LX2
LX2
PGND
PGND
COMP2
FB
1V25
SS2
V5P
WD
ENn
WD
ADJ
WD
IN
Package LV, 38-Pin eTSSOP
Pin-out Diagram


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