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AS8C401825 Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation |
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AS8C401825 Datasheet(HTML) 9 Page - Alliance Semiconductor Corporation |
9 / 19 page 9 AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial Temperature Range 9 Linear Burst Sequence Table ( LBO=VSS) Synchronous Write Function Truth Table (1, 2) Asynchronous Truth Table (1) Interleaved Burst Sequence Table ( LBO=VDD) NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. BW3 and BW4 are not applicable for the AS8C401825. 3. Multiple bytes may be selected during the same cycle. NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. Operation GW BWE BW1 BW2 BW3 BW4 Read H H XXXX Read H L HHHH Write all Bytes L XXXXX Write all Bytes H LLLLL Write Byte 1(3) H L L HHH Write Byte 2(3) HL HL H H Write Byte 3(3) HL H HL H Write Byte 4(3) H L HHH L 5280 tbl 12 Operation(2) OE ZZ I/O Status Power Read L L Data Out Active Read H L High-Z Active Write X L High-Z – Data In Active Deselected X L High-Z Standby Sleep Mode X H High-Z Sleep 5280 tbl 13 Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 000 11 0 11 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 111 00 1 00 5280 tbl 14 Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 000 11 0 11 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 11 000 11 0 5280 tbl 15 |
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