AS7C316098B

Rev. 1.0

1024K X 16 BIT HIGH SPEED CMOS SRAM

Confidential

8

Rev1.0 – June 2014

Dout

Din

Data Valid

(4)

High-Z

WE#

LB#,UB#

CE#

Address

CE2

Notes :

1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions.

2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low.

on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in

a high impedance state.