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581G-02LFT Datasheet(PDF) 3 Page - Integrated Device Technology |
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581G-02LFT Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 10 page ICS581-01/02 ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER ZDB AND MULTIPLEXER IDT® ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER 3 ICS581-01/02 REV M 110216 Pin Descriptions Device Operation The ICS581-01 and ICS581-02 are very similar. Following is a description of the operation of the ICS581-01 and the differences of the ICS581-02. The ICS581-01 is a PLL-based, zero delay, clock multiplexer. The device consists of an input multiplexer controlled by SELA that selects between two clock inputs. The output of the mux drives the reference input of a phase locked loop. The other input to the PLL comes from a feedback input pin called FBIN. The output of the PLL drives four low skew outputs. These chip outputs are therefore buffered versions of the selected input clock with zero delay and 50/50 duty cycle. For correct operation, one of the clock outputs must be connected to FBIN. In this datasheet, CLK4 is shown as the feedback, but any one of the four clock outputs can be used. If output termination resistors are used, the feedback should be connected before the resistor. It is a property of the PLL used on this chip that it will align rising edges on FBIN and either INA or INB (depending on SELA). Since FBIN is connected to a clock output, this means that the outputs appear to align with the input with zero delay. When the input select (SELA) is changed, the output clock will change frequency and/or phase until it lines up with the new input clock. This occurs in a smooth, gradual manner without any short pulses or glitches and will typically take a few tens of microseconds. The part must be configured to operate in the correct frequency range. The table on page two gives the recommended range. The four low skew outputs are controlled by two output enable pins that allow either one, three, or four simultaneous outputs. If both OE pins are low, the PLL is powered down. Note that the clock driving the FBIN pin must not be tri-stated unless the PLL is powered down. Otherwise the Pin Number Pin Name Pin Type Pin Description 1 S0 Input Select 0 for frequency range. See table. Internal pull-up. 2 S1 Input Select 1 for frequency range. See table. Internal pull-up. 3 VDD Power Power Supply. Connect to +3.3 V or +5 V. 4 INA Input Input Clock A. 5 INB Input Input Clock B. 6 GND Power Connect to ground. 7 FBIN Input Feedback input. Connect to a clock output. 8 OE0 Input Output enable 0. See table. Internal pull-up. 9 OE1 Input Output enable 1. See table. Internal pull-up. 10 GND Power Connect to ground. 11 CLK4 Output Low skew clock output. 12 CLK3 Output Low skew clock output. 13 CLK2 Output Low skew clock output. 14 CLK1 Output Low skew clock output. 15 VDD Power Power Supply. Connect to +3.3 V or +5 V. 16 (-01) SELA Input Mux select. Selects INA when high. Internal pull-up. 16 (-02) DIV Input Timeout select. See table. Internal pull-up. |
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