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84329-01 Datasheet(PDF) 3 Page - Integrated Device Technology |
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84329-01 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 20 page 84329AM-01 www.idt.com REV. D APRIL 9, 2014 3 84329-01 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS Symbol Parameter Test Conditions Minimum Typical Maximum Units C IN Input Capacitance 4 pF R PULLUP Input Pullup Resistor 51 k Ω R PULLDOWN Input Pulldown Resistor 51 k Ω Name Type Description M0, M1, M2, M3, M4, M5, M6, M7, M8 Input Pullup M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input. LVCMOS / LVTTL interface levels. N0, N1 Input Pullup Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. V EE Power Negative supply pins. TEST Output Test output which is used in the serial mode of operation. LVCMOS / LVTTL interface levels. V CC Power Core supply pins. nFOUT, FOUT Output Differential output for the synthesizer. 3.3V LVPECL interface levels. S_CLOCK Input Pulldown Clocks the serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. S_LOAD Input Pulldown Controls transition of data from shift register into the M divider. LVCMOS / LVTTL interface levels. V CCA Power Analog supply pin. nc Unused No connect. XTAL1, XTAL2 Input Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. nP_LOAD Input Pullup Parallel load input. Determines when data present at M8:M0 is loaded into the M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. |
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