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AS4C256M8D3-15BIN Datasheet(PDF) 7 Page - Alliance Semiconductor Corporation |
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AS4C256M8D3-15BIN Datasheet(HTML) 7 Page - Alliance Semiconductor Corporation |
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7 / 82 page  AS4C256M8D3 Confidential 7 Rev. 3.0 Aug. /2014 DM Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. DM has an optional use as TDQS on the x8. DQ0 – DQ7 Input / Output Data I/O: The DQ0-DQ7 input and output data are synchronized with positive and negative edges of DQS and DQS#. The I/Os are byte-maskable during Writes. ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS#, DM/TDQS and TDQS# signal. (When TDQS is enabled via Mode Register A11=1 in MR1) The ODT pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT. RESET# Input Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD VDD Supply Power Supply: +1.5V 0.075V VSS Supply Ground VDDQ Supply DQ Power: +1.5V 0.075V. VSSQ Supply DQ Ground VREFCA Supply Reference voltage for CA VREFDQ Supply Reference voltage for DQ ZQ Supply Reference pin for ZQ calibration. NC - No Connect: These pins should be left unconnected. |
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