Signal and Timing Description

General Description

The 1Gbit mobile DDR is a 128M byte mobile DDR SDRAM. It consists of four banks. Each bank is organized as 8192

rows x 1024 columns x 32 bits.

Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate command, which is

then followed by a Read or Write command. The address bits registered coincident with the Activate command are used

to select the bank and the row to be accessed. BA1 and BA0 select the bank, address bits A13.. A0 select the row.

Address bits A9.. A0 registered coincident with the Read or Write command are used to select the starting column loca-

tion for the burst access.

The regular Single Data Rate SDRAM read and write cycles only use the rising edge of the external clock input. For the

mobile SDRAM the special signals DQSx (Data Strobe) are used to mark the data valid window. During read bursts, the

data valid window coincides with the high or low level of the DQSx signals. During write bursts, the DQSx signal marks

the center of the valid data window. Data is available at every rising and falling edge of DQSx, therefore the data transfer

rate is doubled.

For Read accesses, the DQSx signals are aligned to the clock signal CLK.

Special Signal Description

Clock Signal

The mobile DDR operates with a differential clock (CLK and CLK) input. CLK is used to latch the address and command

signals. Data input and DMx signals are latched with DQSx. The minimum and maximum clock cycle time is defined by

Command Inputs and Addresses

Like single data rate SDRAMs, each combination of RAS, CAS and WE input in conjunction with CS input at a rising

edge of the clock determines a mobile DDR command.

Command and Address Signal Timing

Valid

Valid

CLK, CLK#

Address,

CS#, RAS#,

CAS#, WE#,

CKE

VIH

VTT

VIL

VIH

VIL

 

 

 

 

AS4C32M32MD1

Confidential

-8-

Rev.1.0 Sep.2014