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TSE2004GB2C0NCG Datasheet(PDF) 9 Page - Integrated Device Technology

Part # TSE2004GB2C0NCG
Description  DDR4 Temperature Sensor with Integrated 4Kbit EEPROM for Memory Module
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

TSE2004GB2C0NCG Datasheet(HTML) 9 Page - Integrated Device Technology

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©2017 Integrated Device Technology, Inc.
May 15, 2017
TSE2004GB2C0 Datasheet
Start Condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must
precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data (SDA), while Serial Clock (SCL) is stable and driven High. A Stop condition terminates
communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the SPD into Standby mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle for the
SPD. Neither of these conditions changes the operation of the TS section.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be the bus master or the slave device,
releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
No Acknowledge Bit (NACK)
The no-acknowledge bit is used to indicate the completion of a block read operation, or an attempt to modify a write-protected register.
The bus master releases Serial Data (SDA) after sending eight bits of data and during the 9th clock pulse period, and does not pull Serial
Data (SDA) Low.
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial
Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial
Clock (SCL) is driven Low.
Memory Addressing
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following, the bus
master sends the Device Select Code (Table 3) on Serial Data (SDA) most significant bit first).


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