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IDT82V3389 Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT82V3389 Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 156 page  List of Figures 8 June 13, 2012 Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11 Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12 Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 21 Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 22 Figure 5. External Fast Selection ................................................................................................................................................................................ 24 Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 25 Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 31 Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 32 Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 40 Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 40 Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 41 Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 41 Figure 13. 1 UI Late Frame Sync 2K/8K Pulse Input Signal Timing ............................................................................................................................ 41 Figure 14. On Target Frame Sync 2K/8K Pulse Input Signal Timing .......................................................................................................................... 41 Figure 15. Physical Connection Between Two Devices .............................................................................................................................................. 43 Figure 16. IDT82V3389 Power Decoupling Scheme ................................................................................................................................................... 45 Figure 17. Typical Application ...................................................................................................................................................................................... 46 Figure 18. EPROM Access Timing Diagram ............................................................................................................................................................... 49 Figure 19. Multiplexed Read Timing Diagram ............................................................................................................................................................. 50 Figure 20. Multiplexed Write Timing Diagram .............................................................................................................................................................. 51 Figure 21. Intel Read Timing Diagram ......................................................................................................................................................................... 52 Figure 22. Intel Write Timing Diagram ......................................................................................................................................................................... 53 Figure 23. Motorola Read Timing Diagram .................................................................................................................................................................. 54 Figure 24. Motorola Write Timing Diagram .................................................................................................................................................................. 55 Figure 25. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 56 Figure 26. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 56 Figure 27. Serial Write Timing Diagram ....................................................................................................................................................................... 57 Figure 28. JTAG Interface Timing Diagram ................................................................................................................................................................. 59 Figure 29. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................. 132 Figure 30. Recommended PECL Input Port Line Termination .................................................................................................................................. 135 Figure 31. Recommended PECL Output Port Line Termination ................................................................................................................................ 135 Figure 32. Recommended LVDS Input Port Line Termination .................................................................................................................................. 137 Figure 33. Recommended LVDS Output Port Line Termination ................................................................................................................................ 137 Figure 34. Example of Single-Ended Signal to Drive Differential Input ..................................................................................................................... 138 Figure 35. Output Wander Generation (TDEV) ......................................................................................................................................................... 143 Figure 36. Output Wander Generation (MTIE) .......................................................................................................................................................... 143 Figure 37. Input / Output Clock Timing ...................................................................................................................................................................... 144 Figure 38. Output Clock Timing ................................................................................................................................................................................. 146 Figure 39. 100-Pin EQG Package Dimensions (a) (in Millimeters) ............................................................................................................................ 152 Figure 40. 100-Pin EQG Package Dimensions (b) (in Millimeters) ............................................................................................................................ 153 Figure 41. EQG100 Recommended Land Pattern with Exposed Pad (in Millimeters) .............................................................................................. 154 List of Figures DATASHEET |
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