6.42

6

IDT71128 CMOS Static RAM

1 Meg (256K x 4-bit) Revolutionary Pinout

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing

NOTES:

1. A write occurs during the overlap of a LOW

CS and a LOW WE.

2.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the

5. Transition is measured ±200mV from steady state.

ADDRESS

CS

WE

3483 drw 07

(5)

(3)

(3)

(2)

(5)

(5)

HIGH IMPEDANCE

CS

ADDRESS

WE

3483 drw 08