ICS853S54AKI May 27, 2017

2

©2017 Integrated Device Technology, Inc.

ICS853S54I Data Sheet

DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Function Tables

Table 3A. Control Input Function Table, (Bank A)

Table 3B. Control Input Function Table, (Bank B)

Number

Name

Type

Description

1, 2

QB0, nQB0

Output

Differential output pair. LVPECL/ECL interface levels.

3, 4

QB1, nQB1

Output

Differential output pair. LVPECL/ECL interface levels.

5

PCLKB

Input

Pulldown

Non-inverting LVPECL/ECL differential clock input.

6

nPCLKB

Input

Pullup/

Pulldown

7

CLK_SELB

Input

Pulldown

Clock select pin for QBx outputs. When HIGH, selects QB1/nQB1 outputs.

When LOW, selects QB0/nQB0 outputs. LVCMOS/LVTTL interface levels.

Power

Negative supply pin.

9

nPCLKA1

Input

Pullup/

Pulldown

10

PCLKA1

Input

Pulldown

Non-inverting LVPECL/ECL differential clock input.

11

nPCLKA0

Input

Pullup/

Pulldown

12

PCLKA0

Input

Pulldown

Non-inverting LVPECL/ECL differential clock input.

13

Power

Positive supply pin.

14

CLK_SELA

Input

Pulldown

Clock select pin for QA output. When HIGH, selects QA output. When LOW,

selects nQA output. LVCMOS/LVTTL interface levels.

15, 16

nQA, QA

Output

Differential output pair. LVPECL/ECL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

2

pF

Input Pullup Resistor

37.5

k



RPullup/Pulldown Resistor

37.5

k



Bank A

Control Input

Outputs

CLK_SELA

QA, nQA

0 (default)

Selects PCLKA0, nPCLKA0

1

Selects PCLKA1, nPCLKA1

Bank B

Control Input

Outputs

CLK_SELB

QB0, nQB0

QB1, nQB1

0 (default)

Follows PCLKB input

Logic Low

1

Logic Low

Follows PCLKB input