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IDT70V7399S166BF Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT70V7399S166BF Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 22 page  6.42 2 IDT70V7399S High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V7399 is a high-speed 128Kx18 (2Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 2Kx18 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx18 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data Pin Configuration(1,2,3,4) NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. A17 VSS B17 NC C17 VSS D17 I/O7R E16 VSS E17 NC D16 I/O7L C16 NC B16 I/O8L A16 NC A15 OPTL B15 VDDQR C15 I/O8R D15 VDDQL E15 NC E14 I/O6L D14 NC D13 VDD C12 A6L C14 VDD B14 VSS A14 A0L A12 CNTENL B12 A5L C11 R/WL D12 A3L D11 REPEATL C10 VSS B11 ADSL A11 CLKL D8 LBL C8 UBL A9 NC D9 VDD C9 CE1L B9 CE0L D10 OEL C7 A10L B8 NC A8 A8L B13 A1L A13 A4L A10 VDD D7 A7L B7 A9L A7 BA1L B6 BA2L C6 BA3L D6 BA0L A5 NC B5 NC C5 NC D5 BA4L A4 TDO B4 TDI C4 PL/FTL D4 NC A3 VSS B3 NC C3 VDDQR D3 I/O10L D2 VSS C2 I/O9R B2 VSS A2 NC A1 IO9L B1 NC C1 VDDQL D1 NC E1 I/O11L E2 NC E3 VDDQR E4 I/O10R F1 VDDQL F2 I/O11R F3 NC F4 VSS G1 NC G2 VSS G3 I/O12L G4 NC H1 VDD H2 NC H3 VDDQR H4 I/O12R J1 VDDQL J2 VDD J3 VSS J4 VSS K1 I/O14R K2 VSS K3 I/O13R K4 VSS L1 NC L2 I/O14L L3 VDDQR L4 I/O13L M1 VDDQL M2 NC M3 I/O15R M4 VSS N1 NC N2 VSS N3 NC N4 I/O15L P1 I/O16R P2 I/O16L P3 VDDQR P4 NC R1 VSS R2 NC R3 I/O17R R4 TCK T1 NC T2 I/O17L T3 VDDQL T4 TMS U1 VSS U2 NC U3 PL/FTR U4 NC P5 TRST R5 NC U6 BA0R P12 CNTENR P8 A8R U10 OER P9 NC R8 NC T8 UBR U9 VDD P10 VDD T11 R/WR U8 LBR P11 CLKR R12 A5R T12 A6R U12 A3R P13 A4R P7 BA1R R13 A1R T13 A2R U13 A0R R6 BA2R T5 NC U7 A7R U14 VDD T14 VSS R14 VSS P14 NC P15 I/O1L R15 VDDQL T15 NC U15 OPTR U16 NC U17 I/O0L T16 VSS T17 NC R17 VDDQR R16 I/O0R P17 NC P16 VSS N17 I/O2L N16 NC N15 VDDQL N14 I/O1R M17 VDDQR M16 I/O2R M15 NC M14 VSS L17 I/O4L L16 VSS L15 I/O3L L14 NC K17 VSS K16 I/O4R K15 VDDQL K14 I/O3R J17 VDDQR J16 VSS J15 VDD J14 VSS H17 I/O5R H16 VSS H15 NC H14 VDD G17 NC G16 I/O5L G15 VDDQL G14 NC F17 VDDQR F16 NC F14 VSS 70V7399BF BF-208(5) 208-Pin fpBGA Top View(6) F15 I/O6R R9 CE0R R11 ADSR T6 BA3R T9 CE1R A6 BA5L B10 VSS C13 A2L P6 BA5R R10 VSS R7 A9R T10 VSS T7 A10R U5 BA4R 5630 drw 02c , 11/20/01 register, the IDT70V7399 has been optimized for applications having unidirectionalorbidirectionaldataflowinbursts.Anautomaticpowerdown feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The dual chip enables also facilitatedepthexpansion. The 70V7399 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device(VDD) remains at 3.3V. Please refer also to the functional description on page 19. |
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