AS4C128M8D3L-12BIN datasheet(8/88 Pages) ALSC

Part #	AS4C128M8D3L-12BIN

Description	internal banks for concurrent operation

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Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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1Gb DDR3L – AS4C128M8D3L

Confidential

8

Rev. 2.0

Aug. /2014

Operation Mode Truth Table

Table 4. Truth Table (Note (1), (2))

Command

State CKEn-1(3) CKEn DM BA0-2 A10/AP

A0-9, 11, 13

A12/BC#

CS#

RAS# CAS#

WE#

BankActivate

Idle(4)

H

X

V

Row address

L

H

Single Bank Precharge

Any

H

X

V

L

V

L

H

L

All Banks Precharge

Any

H

X

V

H

V

L

H

L

Write (Fixed BL8 or BC4)

Active(4)

H

X

V

L

V

L

H

L

Write (BC4, on the fly)

Active(4)

H

X

V

L

V

L

H

L

Write (BL8, on the fly)

Active(4)

H

X

V

L

V

H

L

H

L

Write with Autoprecharge

(Fixed BL8 or BC4)

Active(4)

H

X

V

H

V

L

H

L

Write with Autoprecharge

(BC4, on the fly)

Active(4)

H

X

V

H

V

L

H

L

Write with Autoprecharge

(BL8, on the fly)

Active(4)

H

X

V

H

V

H

L

H

L

Read (Fixed BL8 or BC4)

Active(4)

H

X

V

L

V

L

H

L

H

Read (BC4, on the fly)

Active(4)

H

X

V

L

V

L

H

L

H

Read (BL8, on the fly)

Active(4)

H

X

V

L

V

H

L

H

L

H

Read with Autoprecharge

(Fixed BL8 or BC4)

Active(4)

H

X

V

H

V

L

H

L

H

Read with Autoprecharge

(BC4, on the fly)

Active(4)

H

X

V

H

V

L

H

L

H

Read with Autoprecharge

(BL8, on the fly)

Active(4)

H

X

V

H

V

H

L

H

L

H

(Extended) Mode Register Set

Idle

H

X

V

OP code

L

No-Operation

Any

H

X

V

L

H

Device Deselect

Any

H

X

H

X

Burst Stop

Active(5)

H

X

L

H

L

Refresh

Idle

H

X

V

L

H

SelfRefresh Entry

Idle

H

L

X

V

L

H

SelfRefresh Exit

Idle

L

H

X

H

X

V

L

H

Power Down Mode Entry

Idle

H

L

X

H

X

V

L

H

Power Down Mode Exit

Any

L

H

X

H

X

V

L

H

Data Input Mask Disable

Active

H

X

L

X

Data Input Mask Enable(6)

Active

H

X

H

X

ZQ Calibration Long

Idle

H

X

H

X

L

H

L

ZQ Calibration Short

Idle

H

X

L

X

L

H

L

NOTE 1: V=Valid data, X=Don't Care, L=Low level, H=High level

NOTE 2: CKEn signal is input level when commands are provided.

NOTE 3: CKEn-1 signal is input level one clock cycle before the commands are provided.

NOTE 4: These are states of bank designated by BA signal.

NOTE 5: Device state is 4, and 8 burst operation.

NOTE 6: LDM and UDM can be enabled respectively.

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