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5V41285NLGI8 Datasheet(PDF) 9 Page - Integrated Device Technology |
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5V41285NLGI8 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 17 page IDT5V41285 2 OUTPUT PCIE GEN1/2 SYNTHESIZER IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 9 IDT5V41285 MAY 8, 2017 AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1 Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85 C Note 1: Test setup is RS=33RP=50 with CL=2 pF, Rr = 475 (1%). Note 2: Measurement taken from a single-ended waveform. Note 3: Measurement taken from a differential waveform. Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal. Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high. Electrical Characteristics - Differential Phase Jitter Note 1. Guaranteed by design and characterization, not 100% tested in production. Note 2. See http://www.pcisig.com for complete specs. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 25 MHz Output Frequency HCSL termination 25 200 MHz LVDS termination 25 100 MHz Output High Voltage1,2 VOH HCSL 850 mV Output Low Voltage1,2 VOL HCSL -150 mV Crossing Point Voltage1,2 Absolute 250 550 mV Crossing Point Voltage1,2,4 Variation over all edges 140 mV Jitter, Cycle-to-Cycle1,3 80 ps Frequency Synthesis Error All outputs 0 ppm Rise Time1,2 tOR From 0.175 V to 0.525 V 175 700 ps Fall Time1,2 tOF From 0.525 V to 0.175 V 175 700 ps Rise/Fall Time Variation1,2 125 ps Output to Output Skew 50 ps Duty Cycle1,3 45 55 % Output Enable Time5 All outputs 50 100 ns Output Disable Time5 All outputs 50 100 ns Stabilization Time tSTABLE From power-up VDD=3.3 V 1.8 ms Parameter Symbol Conditions Min Typ Max Units Notes Jitter, Phase tjphasePLL PCIe Gen1 32 86 ps (p-p) 1,2 tjphaseLO PCIe Gen2, 10 kHz < f < 1.5 MHz 0.8 3 ps (RMS) 1,2 tjphaseHIGH PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz) 2.3 3.1 ps (RMS) 1,2 |
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