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8745BYILF Datasheet(PDF) 2 Page - Integrated Device Technology |
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8745BYILF Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 20 page ICS8745BYI REVISION D JUNE 11, 2009 2 ©2009 Integrated Device Technology, Inc. ICS8745BI Data Sheet 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Number Name Type Description 1, 2, 12, 29 SEL0, SEL1, SEL2 SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input. 5 CLK1 Input Pulldown Non-inverting differential clock input. 6 nCLK1 Input Pullup Inverting differential clock input. 7 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK1,nCLK1. When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels. 8 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 9, 32 VDD Power Core supply pins. 10 FBIN Input Pullup Inverting differential feedback input to phase detector for regenerating clocks with “Zero Delay.” 11 FBIN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating clocks with “Zero Delay.” 13, 19, 25 GND Power Power supply ground. 14, 15 nQ0/Q0 Output Differential output pair. LVDS interface levels. 16, 22, 28 VDDO Power Output supply pins. 17, 18 nQ1/Q1 Output Differential output pair. LVDS interface levels. 20, 21 nQ2/Q2 Output Differential output pair. LVDS interface levels. 23, 24 nQ3/Q3 Output Differential output pair. LVDS interface levels. 26, 27 nQ4/Q4 Output Differential output pair. LVDS interface levels. 30 VDDA Power Analog supply pin. 31 PLL_SEL Input Pullup PLL select. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels. Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4pF RPULLUP Input Pullup Resistor 51 k Ω RPULLDOWN Input Pulldown Resistor 51 k Ω |
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