REVISION E 05/19/14

3

FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

ICS251 DATASHEET

PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

1) The 0.01µF decoupling capacitor should be mounted on the

component side of the board as close to the VDD pin as

possible. No vias should be used between the decoupling

capacitor and VDD pin. The PCB trace to VDD pin should be

kept as short as possible, as should the PCB trace to the

ground via. Distance of the ferrite bead and bulk decoupling

from the device is less critical.

2) The external crystal should be mounted just next to the

device with short traces. The X1 and X2 traces should not be

routed next to each other with minimum spaces, instead they

should be separated and away from other traces.

3) To minimize EMI, the 33

 series termination resistor (if

needed) should be placed close to the clock output.

4) An optimum layout is one with all components on the same

side of the board, minimizing vias through other signal layers.

Other signal traces should be routed away from the ICS251.

This includes signal traces just underneath the device, or on

layers adjacent to the ground plane layer used by the device.

ICS251 Configuration Capabilities

The architecture of the ICS251 allows the user to easily

configure the device to a wide range of output frequencies, for

a given input reference frequency.

The frequency multiplier PLL provides a high degree of

precision. The M/N values (the multiplier/divide values

available to generate the target VCO frequency) can be set

within the range of M = 1 to 2048 and N = 1 to 1024.

The ICS251 also provides separate output divide values, from

2 through 20, to allow the two output clock banks to support

widely differing frequency values from the same PLL.

Each output frequency can be represented

as:

Output Drive Control

The ICS251 has two output drive settings. Low drive should

be selected when outputs are less than 100 MHz. High drive

should be selected when outputs are greater than 100 MHz.

(Consult the AC Electrical Characteristics for output rise and

fall times for each drive option.)

IDT VersaClock Software

IDT applies years of PLL optimization experience into a user

friendly software that accepts the user’s target reference clock

and output frequencies and generates the lowest jitter, lowest

power configuration, with only a press of a button. The user

does not need to have prior PLL experience or determine the

optimal VCO frequency to support multiple output

frequencies.

VersaClock software quickly evaluates accessible VCO

frequencies with available output divide values and provides

an easy to understand, bar code rating for the target output

frequencies. The user may evaluate output accuracy,

performance trade-off scenarios in seconds.

Spread Spectrum Modulation

The ICS251 utilizes frequency modulation (FM) to distribute

energy over a range of frequencies. By modulating the output

clock frequencies, the device effectively lowers energy across

a broader range of frequencies; thus, lowering a system’s

electro-magnetic interference (EMI). The modulation rate is

the time from transitioning from a minimum frequency to a

maximum frequency and then back to the minimum.

Spread Spectrum Modulation can be applied as either “center

spread” or “down spread”. During center spread modulation,

the deviation from the target frequency is equal in the positive

and negative directions. The effective average frequency is

equal to the target frequency. In applications where the clock

is driving a component with a maximum frequency rating,

down spread should be applied. In this case, the maximum

frequency, including modulation, is the target frequency. The

effective average frequency is less than the target frequency.

The ICS251 operates in both center spread and down spread

modes. For center spread, the frequency can be modulated

between +/- 0.125% to +/-2.0%. For down spread, the

frequency can be modulated between -0.25% to -4.0%.

Both output frequency banks will utilize identical spread

spectrum percentage deviations and modulation rates, if a

common VCO frequency can be identified.

Spread Spectrum Modulation Rate

The spread spectrum modulation frequency applied to the

output clock frequency may occur at a variety of rates. For

applications requiring the driving of “down-circuit” PLLs, Zero

Delay Buffers, or those adhering to PCI standards, the spread

spectrum modulation rate should be set to 30-33 kHz. For

other applications, a 120 kHz modulation option is available.

OutputFreq

REFFreq

OutputDivide

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M

N

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