873991

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REV. A 8/25/15

3

873991

Number

Name

Type

Description

1V

EE

Power

Negative supply pin.

2

MR

Input

Pulldown

Active High Master Reset. When logic HIGH, the internal dividers are

reset causing the true outputs (Qx) to go low and the inverted outputs

(nQx) to go high. When logic LOW, the internal dividers and the outputs

are enabled. LVCMOS/LVTTL interface levels.

3

PLL_EN

Input

Pulldown

PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH, PLL

is in bypass mode. LVCMOS/LVTTL interface levels.

4

REF_SEL

Input

Pulldown

Selects between the different reference inputs as the PLL reference

source. When logic LOW, selects PCLK/nPCLK. When logic HIGH, selects

TEST_CLK. LVCMOS/LVTTL interface levels.

5

6

7

FSEL_FB2

FSEL_FB1

FSEL_FB0

Input

Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels.

8

TEST_CLK

Input

Pulldown LVCMOS/LVTTL test clock input.

9

PCLK

Input

Pulldown Non-inverting differential LVPECL clock input.

10

nPCLK

Input

Pullup/

Pulldown

Inverting differential LVPECL clock input. V

11

V

CC

Power

Core supply pin.

12

EXT_FB

Input

Pulldown External feedback input.

13

nEXT_FB

Input

Pullup/

Pulldown

External feedback input. t. V

14

V

CCA

Power

Analog supply pin.

15

16

nQFB

QFB

Output

Differential feedback output pair. LVPECL Interface levels.

17, 22, 30, 42

V

CCO

Power

Output supply pins.

18, 19

nQD0, QD0

Output

Differential output pair. LVPECL interface levels.

20, 21

nQD1, QD1

Output

Differential output pair. LVPECL interface levels.

23, 24

nQC0, QC0

Output

Differential output pair. LVPECL interface levels.

25, 26

nQC1, QC1

Output

Differential output pair. LVPECL interface levels.

27

33

36

39

FSEL3

FSEL2

FSEL1

FSEL0

Input

Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.

28, 29

nQC2, QC2

Output

Differential output pair. LVPECL interface levels.

31, 32

nQB0, QB0

Output

Differential output pair. LVPECL interface levels.

34, 35

nQB1, QB1

Output

Differential output pair. LVPECL interface levels.

37, 38

nQB2, QB2

Output

Differential output pair. LVPECL interface levels.

40, 41

nQB3, QB3

Output

Differential output pair. LVPECL interface levels.

43, 44

nQA0, QA0

Output

Differential output pair. LVPECL interface levels.

45, 46

nQA1, QA1

Output

Differential output pair. LVPECL interface levels.

47, 48

nQA2, QA2

Output

Differential output pair. LVPECL interface levels.

49, 50

nQA3, QA3

Output

Differential output pair. LVPECL interface levels.

51

SYNC_SEL

Input

Pulldown

SYNC output select pin. When LOW, the SYNC otuput follows the timing

diagram (page 5). When HIGH, QD output follows QC output.

52

VCO_SEL

Input

Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.