Rev A 8/14/15

5

FEMTOCLOCK™ DUAL VCXO VIDEO PLL

810001-22 DATA SHEET

Table 3B. Output Frequency Table (Dual PLL Mode)

NOTE: Use the VCXO-PLL mode to achieve output frequencies of 27MHz or 26.973MHz. See Table 3G.

Table 3C. CLK_SEL Function Table

Table 3D. MR Master Reset Function Table

Table 3E. FemtoCLock PLL Feedback Divider Function Table

FemtoClock Look-up Table

MF

N1

N0

27MHz

0

0

0

148.5000

0

0

1

74.2500

0

1

0

49.5000

0

1

1

33.0000

1

0

0

162.0000

1

0

1

81.0000

1

1

0

54.0000

1

1

1

36.0000

26.973MHz

0

0

0

148.3515

0

0

1

74.1758

0

1

0

49.4505

0

1

1

32.9670

1

0

0

161.8382

1

0

1

80.9191

1

1

0

53.9461

1

1

1

35.9640

Input

Operation

CLK_SEL

0 (default)

Selects CLK0 as PLL reference input.

1

Selects CLK1 as PLL reference input.

Input

Operation

MR

0 (default)

Normal operation, internal dividers and the output Q are enabled.

1

Internal dividers are reset. Q output is in logic low state (with OE = 1).

Input

Operation

MF

0 (default)

Selects MF = 22. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 22.

1

Selects MF = 24. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 24.